Abstract: A dynamic circuit has an improved noise margin that is not solely dominated by a threshold voltage of the transistors from which it is comprised. A transistor is utilized such that a ratio of the width of the feedback device to a pull-down transistor in a dynamic circuit determines when the pull-down transistor becomes active and conducts current. Therefore, rather than having a low threshold voltage which may be significantly and substantially impacted by the presence of noise on an input signal, beta ratioed transistors are implemented to give greater noise immunity and increase a circuit's ability to tolerate noisy input lines. Furthermore, a structure of the dynamic circuit of the dynamic circuit preserves the functionality of that circuit. More specifically, after a dynamic node of a circuit of the present invention has been discharged, the node remains discharged and is only precharged again when a subsequent clock pulse occurs.

Abstract: A dynamic switching circuit for use in a domino circuit array is disclosed. The dynamic switching circuit includes a charge-saving transistor for preventing charge stored on the dynamic circuit's output node from discharging to ground. The charge stored on the output node is then fed back to a precharge control transistor to charge the dynamic node during the subsequent precharge/evaluate cycle.

Abstract: Control circuitry is used to select M entries from an N-entry storage array by viewing the array from both ends. Beginning at both ends of the array, particular bit values or entry content is looked for by the control logic. Once found at both ends, these entries are then used to produce control signals to be sent to a pair of muxes to remove these entries. Then a subset of the original array consisting of the remaining entries of the array is then iterated upon by a similar set of control circuitry for finding and removing the next M entries from the storage array.

Abstract: Comparative circuits 10, 100 for comparing a first address comprising at least two bits to a second address comprising an equal number of corresponding bits as the first address to determine if the first address equals or does not equal the second address as disclosed. Comparative circuits 10, 100 include two bit to four bit encoders for encoding each two bits of the first address into a first four bit representation, wherein each bit has an on state and an off state and only one of the four bits is in the on state at one time, each two bits of the second address into a second four bit representation, wherein each bit corresponds to a bit from the first four bit representation. The four bit representations are then inputted into the remainder of the comparator circuits 10, 100.