Abstract: Radio-frequency (RF) apparatus includes receiver analog circuitry that receives an RF signal and provides at least one digital signal to receiver digital circuitry that functions in cooperation with the receiver analog circuitry. The receiver analog circuitry and the receiver digital circuitry are partitioned so that interference effects between the receiver analog circuitry and the receiver digital circuitry tend to be reduced.

Abstract: A method and apparatus for synthesizing high-frequency signals is disclosed that overcomes integration problem associated with prior implementations while meeting demanding phase noise and other impurity requirements. In one embodiment, a phase-locked loop (PLL) frequency synthesizer is disclosed having a voltage controlled oscillator (VCO) with a variable capacitance that includes a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance, and the continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance.

Abstract: A method and apparatus for synthesizing high-frequency signals is disclosed that overcomes integration problem associated with prior implementations while meeting demanding phase noise and other impurity requirements. In one embodiment, a phase-locked loop (PLL) frequency synthesizer is disclosed having a voltage controlled oscillator (VCO) with a variable capacitance that includes a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance, and the continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance.

Abstract: A receive path implementation for an intermediate frequency (IF) transceiver is disclosed that provides increased signal processing integrity and accuracy with an efficient and improved design. A complex filter for a bandpass delta-sigma analog-to-digital converter (ADC) provides efficient complex noise shaping with a combination of real and complex filters. An automatic gain control (AGC) amplifier provides a constant bandwidth and zero variation phase shift for all gain levels. Clock adjust circuitry provides a clock signal with a jitter-free edge and a high percentage duty cycle. A fixed-gain input amplifier provides a matched input impedance. A method for choosing design specifications provides improved anti-aliasing properties.

Abstract: A 1-bit discrete time digital-to-analog converter which samples a reference voltage and ground potential onto two charging capacitors during a sample phase of each sampling period, and which transfers the charge on one of the capacitors, as determined by a digital input signal, onto an integrator during a transfer phase of said sampling circuit, draws current from the reference voltages which is independent of the data into the converter. The improvement comprises the addition of at least one phase to each sampling period so that the current drawn from said reference voltage is essentially independent of said digital input signal.

Abstract: An analog resistive touch screen is powered by a current source responsive to a stored digital control value. The current source is calibrated by comparing the excitation voltage across the touch screen to a desired voltage to produce a comparison signal, and adjusting the digital control value in response to the comparison signal so that the excitation voltage becomes substantially equal to the desired voltage. The power supply can therefore be easily constructed in a low-voltage CMOS integrated circuit having a minimal power consumption without sacrificing touch screen resolution. Preferably the comparison of the excitation voltage to the reference voltage is performed by an analog-to-digital converter that is later used in a normal conversion mode for digitizing the touch screen coordinates.

Abstract: The detrimental nonlinear charging currents from an analog input signal through an anti-aliasing filter into a sampling circuit can be minimized by using primary and secondary inputs to the sampling circuit. The secondary input is turned on before the primary input and the charge required to charge the parasitic capacitance inside the sampling circuit and to replenish the channeling charge lost in the previous cycle is supplied primarily through the secondary input. Immediately after the secondary input is turned off the primary input is connected to the sampling node, and only the charge required to fine tune the signal into the sampling capacitor is drawn through the primary input. Therefore, most of the non-linear charge injection is passed through the secondary input, and the signal passed through the primary input is used to fine tune the voltage levels inside the sampling circuit during the actual sampling operation.

Abstract: An algorithmic converter system includes an algorithmic converter having a loop gain substantially less than two for converting an analog input signal to a redundant digital code; and a digital computation unit for converting the redundant digital code to a digital output signal by computing a polynomial of a radix, said radix being substantially equal to the loop gain, wherein the redundant digital code specifies coefficients of the polynomial. The redundancy extends the analog input conversion range with respect to the voltage reference of the algorithmic converter. Moreover, if the algorithmic converter has a maximum offset of V.sub.offmax, a reference voltage of V.sub.ref, and a loop gain less than 2/(1+V.sub.offmax /V.sub.ref), then loop offset will not cause differential nonlinearities. Nonlinearity is further reduced by digitally compensating for variations in the loop gain.

Abstract: A differential input stage for a data conversion device includes two sections, one section for operating during a high stress portion of a charge transfer operation and one portion for operating during the remainder of the charge transfer operation. The first portion is comprised of two differential transistors (84) and (86) having the sources and bodies thereof connected to a source coupled node and connected through a switch (94) to a current source (92). The drains of transistors (84) and (86) are connected through switches (110) and (112), respectively, to output terminals. During the second half of the charge transfer operation, differential transistors (78) and (88), having the sources and bodies thereof connected to a source coupled node and connected to the current source (92) through a switch (90), are rendered operable with the drains thereof connected through switches (96) and (104), respectively, to the output terminals. Only one of the differential pairs is operable at any one time.

Abstract: Digital linearity correction is obtained by generating a digital calibration signal having at least one frequency component, converting the digital calibration signal to an analog signal, and detecting distortion in the analog signal generated from the calibration signal by nonlinearity to produce a compensation coefficient used to digitally compensate the digital input of the digital-to-analog converter. The compensation coefficient is adjusted in a feedback loop so that the distortion is minimized. Preferably the calibration signal has two frequencies, and the distortion is an intermodulation component having a substantially lower frequency. The intermodulation component, for example, is selected by an R-C low-pass filter, digitized by an analog-to-digital converter, and detected by digital signal processing. The analog-to-digital converter may have low resolution, low dynamic range and a low sampling rate.

Abstract: A ratiometric converter receives an external sense signal and external reference signal and provides an output signal which is proportional to the sense signal and inversely proportional to the reference signal. Electromagnetic interference and noise coupled onto the sense and reference lines are effectively removed by converting the sense signal to a digital signal and converting the reference signal to a digital signal. The digital sense signal is then filtered through a low pass filter to provide a filtered signal, and similarly, the digital reference signal is filtered through a low pass filter to provide a filtered digital reference signal. A divider circuit then divides the filter digital sense signal by the filter digital reference signal to provide the output signal.

Abstract: A 1-bit discrete time digital-to-analog converter which samples a reference voltage and ground potential onto two charging capacitors during a sample phase of each sampling period, and which transfers the charge on one of the capacitors, as determined by a digital input signal, onto an integrator during a transfer phase of said sampling circuit, draws current from the reference voltages which is independent of the data into the converter. The improvement comprises the addition of at least one phase to each sampling period so that the current drawn from said reference voltage is essentially independent of said digital input signal.

Abstract: A switched-capacitor integrator with chopper stabilization performed at the sampling rate virtually eliminates the flicker noise and any low frequency interference generated by the amplifier. The integrator samples the input and then passes the sampled input to the feedback capacitor during each chopping phase of the amplifier to thereby provide a double-sampled integrator. The output of the integrator is sampled at the end of each cycle of the chopping signal.

Abstract: A triple cascoded mirror active load includes three transistors (20), (26) and (28) in a first leg and three transistors (22), (30) and (34) in an output leg connected to an output node (18). The first leg receives a current on an input node (14) on the drain of transistor (20). Transistor (20) has the gate thereof connected to the drain of transistor (26) with the gates of transistors (24) and (30) connected together and to a bias voltage. Transistor (20) is mirrored to transistor (22) by connecting the gates thereof together. Similarly, the gates of transistors (28) and (34) are connected together and also to the node (14). In this manner, the node (14) receives a low impedance on the input thereto, whereas the gate of transistor (22) sees a high impedance thereto and with only two transistors, transistors 26 and 28, disposed in a loop as a ratioed cascoded configuration.

Abstract: A modified lossy integrator digital-to-analog converter includes an amplifier (46) that receives an input on a summing node (48) and provides an output on a node (52). A feedback capacitor (50) is disposed across the input and output and has an output switched-capacitor (54) disposed in parallel therewith to passively distribute the charge thereacross. Switches (60) and (66) are operable to control the switching operation of the capacitor (54). Two input switched capacitors (70) and (94) are controlled by associated switches to switch charge onto the summing node (48) in a first clock cycle .phi..sub.2. A one-bit data stream modulates the operation such that either the charge from the capacitor (78) is dumped onto the summing node (48) or the charge from the capacitor (94) is dumped onto the summing node (48). This operation during the .phi..sub.2 cycle provides an integrated output that is slew-limited.

Abstract: A low drift integrated circuit resistor structure has a forced high end and a forced low end. A sense high connection is located proximate to the force high connection, and a sense low connection is located proximate to the force low connection. The structure also has at least one internal sense connection. This structure can be used in an instrumentation amplifier that includes an operational amplifier which regulates the current between the force high connection and the force low connection in response, in part, to the current sensed in the internal sensing connection of the resistor structure. The sense high connection and the sense low connection form the outputs of the instrumentation amplifier.

Abstract: A low drift integrated circuit resistor structure has a forced high end and a forced low end. A sense high connection is located proximate to the force high connection, and a sense low connection is located proximate to the force low connection. The structure also has at least one internal sense connection. This structure can be used in an instrumentation amplifier that includes an operational amplifier which regulates the current between the force high connection and the force low connection in response, in part, to the current sensed in the internal sensing connection of the resistor structure. The sense high connection and the sense low connection form the outputs of the instrumentation amplifier.

Abstract: A low precision Finite Impulse Response filter (FIR) is provided for filtering in a digital interpolation operation. The interpolation operation includes two steps, a sampling rate conversion operation for interspersing zeroes between samples in an input sequence and a filtering step of filtering out images that result from this operation. The filtering operation utilizes a FIR filter that utilizes low precision filter coefficients that are selected to tune the frequency response such that the low end frequency response including the pass band, the transition band, and the portion of the stop band immediately after the transition band provides a response equivalent to that commensurate with substantially higher precision FIR filter coefficients, with the high frequency end of the stop band gradually increasing.

Abstract: A ratiometric converter is provided that is comprised of a dual converter system utilizing a first converter (36) and a second converter (38). The second converter (38) is operable to receive the input voltage from a load cell (10) on sense lines (12) and (14) and compare them with an internal reference. Similarly, the first A/D converter (36) is operable to receive the reference voltage to the load cell (10) and compare it with the internal reference. The output of each of the converters (36) and (38) is then input to subtraction circuits (78) and (84), respectively, in the digital domain. In a calibration mode, switches (72) and (73) shorts the reference nodes in the load cell (10) together to determine the non-ratiometric offsets., These offsets are then stored in registers (80) and (86) for the reference voltage and the input voltage, respectively.

Abstract: An oversampling analog-to-digital modulator includes an analog loop filter which has a first integrator stage which operates as a continuous time integrator. the second, third, and fourth integrator stages are discrete time or sampling integrators. The continuous time first integrator provides the required thermal noise characteristics of the loop filter while the discrete time integrator stages provide loop stability and transfer characteristics which are advantageous to the overall operation of the analog-to-digital modulator.