Abstract: The present invention features are series of techniques for designing and assembling of large, robust monolithic and monolithic-like flat panel displays. Many techniques originally developed for creating tiled, flat-panel displays having visually imperceptible seams may be advantageously applied to monolithic structures. These techniques include single-sided wiring, two-sided wiring from opposite sides, segmented row and column lines, and reordering row and column lines in fan-out region. Single-sided wiring facilitates the construction of displays with small outlines. By using these techniques, display sharpness and contrast may be improved. In addition, color and luminance balance and uniformity across the display may also be improved.

Abstract: The present invention features methods and apparatuses for sealing tiled, flat-panel displays (FPDs). Tile edges corresponding with the display's perimeter edges are designed with a wide seal. Interior edges, however, have narrow seals in order to maintain the desired, constant, pixel pitch across tile boundaries. In some cases, this invention applies specifically to arrays of tiles 2×2 or less, and, in other cases, to N×M arrays, where N and M are any integer numbers. The tiles are enclosed with top and bottom glass plates, which are sealed with an adhesive bond to the tiles on the outside perimeter of the tiled display. Vertical seams (where tiles meet at the perimeter of the FPD) are sealed with a small amount of polymer. The seal may be constructed between a cover plate and a back plate, sandwiching the tiles. The AMLCD edges may be coated with either a non-permeable material or a polymer having an extremely low permeability (for example, Parylene™).

Abstract: This invention describes fabrication techniques for producing microdisplays suitable for combining into tiled, flat-panel displays having visually imperceptible seams. Assembly techniques to overcome flatness requirements imposed by tiled, flat-panel display assemblies are also described. Edge treatment techniques for individual microdisplays while still part of the silicon die or wafer are also described. The use of these inventive techniques allows the assembly microdisplays into tiled, flat-panel that are appear visually seamless and optically uniform.

Abstract: The present invention features designs of pixels and designs of control features for seals on AMLCD tiles optimized for tiling AMLCD flat panel displays (FPDs) which have visually imperceptible seams. The FPD structure has an image view plane which is continuous and remote from the pixel apertures or image source plane on the inside of the tiles. The image is formed on the view plane by a distributed ultra low magnification flies-eye optical system (a screen) that is integrated with the tiles, effectively excluding and obscuring an image of the seams. The innovations described herein minimize the defects on the perimeter pixels by effectively damming the waviness of the front of the seal near the perimeter pixels on the tiles. Dark space required for the seal between the interior tile edges and active regions of the pixels is decreased, as is the space allocated for wiring thereby increasing the feasible aperture ratios near the mosaic edges and all apertures.

Abstract: A large flat panel display having a plurality of tile display modules with capability in the range of 12 or more lines per inch, being precisely manufactured and aligned such that the interpixel spacing between two adjacent tiles maintains the uniformly periodic spacing of the interpixel spacing within tiles. The display is addressed as a single monolithic display, without reference to the plurality of individual tiles making up the display. All of the interconnections between tiles are located between tiles in the “shadow area”, unless all tiles can have an edge around the periphery of the display. Also disclosed are methods of making and assembling the tiles and the displays.

Abstract: The present invention features flat-panel displays having a mosaic of tiles, and methods of constructing and sealing them. Sealing designs are described to maintain appropriate vacuum levels for FEDs, PFPDs and LCDs. The mosaic of tiles forming a flat-panel display may include subassembly tiles, with each consisting of two, unsealed, substantially parallel plates having a structure positioned between them; these are known as s-tiles. The tiles may be enclosed by a cover plate and backplate. Non-permeable material may be deposited on the cover plate and the backplate, with solderable metal overlaid on the non-permeable material. A metallized, non-permeable spacer/connector is also located between the cover plate and backplate for hermetically sealing the perimeter of the display. A set of electrical-interconnection, metal feed-throughs can also be positioned in the non-permeable spacer/connector.

Abstract: The present invention features methods for assembling arrays of AMLCD tiles into tiled, flat-panel displays having visually imperceptible seams between the tiles. Flowable, polymeric adhesive layers are used between a back substrate, various optical components such as masks and polarizers, the tiles, and a front cover plate. Several unique techniques for establishing and maintaining tile-to-tile registration during assembly of the tiled, flat-panel display are presented.

Abstract: The present invention features methods for assembling arrays of AMLCD tiles into tiled, flat-panel displays having visually imperceptible seams between the tiles. Flowable, polymeric adhesive layers are used between a back substrate, various optical components such as masks and polarizers, the tiles, and a front cover plate. Several unique techniques for establishing and maintaining tile-to-tile registration during assembly of the tiled, flat-panel display are presented.

Abstract: This invention describes tiling structures, methods, and circuits for making large flat-panel displays from an array of microdisplays. The inventive displays overcome the intrinsic size limits of monolithic microdisplays and allow the construction of large area, low cost, high brightness, high contrast magnified view or rear projection flat panel displays having visually imperceptible seams and are optically uniform. A structure wherein multiple microdisplay tiles are mounted on a thermally matched common substrate having inherent temperature control features is described. Additional integrated circuits such as CMOS circuits may be embedded either in the back plane of the microdisplay tiles themselves and/or in the common substrate if the common substrate is made from a suitable semiconductor material. These circuits can provide functions such pixel addressing, image control, or even complete microprocessor functions within the flat-panel display assembly itself.

Abstract: Methods of fabricating AMLCD tiled displays are disclosed, in which variations in the width and the SIP location of seals are controlled. The seals can be controlled by using either a trench or a dam that guides the flow and/or the position of the sealing epoxy between the upper and lower glass plates. The purpose of the dam or trench is to prevent the flow of epoxy towards the pixels of the display. The article made by the above method is a substantially flat-panel display (FPD) having a mosaic of individual, hermetically-sealed tiles disposed adjacent one another upon the lower plate or substrate. The tiles have visually imperceptible seams between them. The individual tiles have pixels and edges that are sealed in position, relative to the substrate, by means of a sealing material, such as an epoxy. The dams or trenches are disposed along the individual tiles, adjacent the pixels.

Abstract: A large flat panel display having a plurality of tile display modules with capability in the range of 12 or more lines per inch, being precisely manufactured and aligned such that the interpixel spacing between two adjacent tiles maintains the uniformly periodic spacing of the interpixel spacing within tiles. The display is addressed as a single monolithic display, without reference to the plurality of individual tiles making up the display. All of the interconnections between tiles are located between tiles in the "shadow area", unless all tiles can have an edge around the periphery of the display. Also disclosed are methods of making and assembling the tiles and the displays.

Abstract: The present invention features methods and apparatuses for sealing tiled, flat-panel displays (FPDs). Tile edges corresponding with the display's perimeter edges are designed with a wide seal. Interior edges, however, have narrow seals in order to maintain the desired, constant, pixel pitch across tile boundaries. In some cases, this invention applies specifically to arrays of tiles 2.times.2 or less, and, in other cases, to N.times.M arrays, where N and M are any integer numbers. The tiles are enclosed with top and bottom glass plates, which are sealed with an adhesive bond to the tiles on the outside perimeter of the tiled display. Vertical seams (where tiles meet at the perimeter of the FPD) are sealed with a small amount of polymer. The seal may be constructed between a cover plate and a back plate, sandwiching the tiles. The AMLCD edges may be coated with either a non-permeable material or a polymer having an extremely low permeability (for example, Parylene.TM.).

Abstract: The present invention features flat-panel displays having a mosaic of tiles, and methods of constructing and sealing them. Sealing designs are described to maintain appropriate vacuum levels for FEDs, PFPDs and LCDs. The mosaic of tiles forming a flat-panel display may include subassembly tiles, with each consisting of two, unsealed, substantially parallel plates having a structure positioned between them; these are known as s-tiles. The tiles may be enclosed by a cover plate and backplate. Non-permeable material may be deposited on the cover plate and the backplate, with solderable metal overlaid on the non-permeable material. A metallized, non-permeable spacer/connector is also located between the cover plate and backplate for hermetically sealing the perimeter of the display. A set of electrical-interconnection, metal feed-throughs can also be positioned in the non-permeable spacer/connector.

Abstract: The present invention features a tiled, substantially flat, panel display having the characteristic of visually imperceptible seams between the tiles for the intended viewing conditions, which include the perception thresholds of the human eye, the view distance, the display brightness and the level of the ambient light. The panel consists of an image source plane having spaced-apart pixels containing light-transmitting elements comprising single or multiple lightvalves. These lightvalves transmit monochromatic light, or primary color light spectra, for example, red, green and blue, in gray-scale and color displays, respectively. Each of the pixels is located along the image source plane at a uniform pitch greater than approximately 0.2 mm. Many adjacently-situated tiles are located in a plane in proximity to the image source plane. Secondary light rays can be controlled via light shields, aperture plates, masks and optical elements.

Abstract: A multi-layer printed circuit board or card including a plurality of circuitized power cores, the circuitized power cores include a layer of an electrically conductive material having a layer of electrically insulating material attached on both sides thereof. The circuitized power cores also include a plurality of plated through holes formed therethrough in substantially the same pattern on each circuitized power core. The circuitized power cores are parallel to each other such that corresponding plated through holes in the two circuitized power cores are co-linear. A plurality of substantially spherical balls are located between the circuitized power cores and are in contact with the corresponding plated through holes on facing cards. The balls have a diameter slightly larger than the opening of the plated through holes and are made of an electrically conductive material.

Abstract: Solder interconnection whereby the gap created by solder connections between an organic substrate and semiconductor device is filled with a composition obtained from curing a thermosetting preparation containing a thermosetting binder; and filler having a maximum particle size of 50 microns.

Abstract: A method for providing precise alignment and positioning of a plurality of flexible circuit members on a common, rigid circuit member. The steps of the method include providing reference points on a support member (e.g., metal frame) which forms part of the common circuit member, accurately determining the precise location of the several contact arrays on the common circuit member's substrate, and providing location apertures from these measurements within the support member to accept precisely located male pins which form part of the flexible circuit members.

Abstract: A composite substrate is fabricated by applying to a glass fiber substrate a liquid sol-gel composition and then sintering the sol-gel to convert it to the glass phase. A polymeric coating is then applied.

Abstract: Solder interconnection whereby the gap created by solder connections between an organic substrate and semiconductor device is filled with a composition obtained from curing a thermosetting preparation containing a thermosetting binder; and filler having a maximum particle size of 50 microns.

Abstract: An electronic packaging structure, and a method of making this structure, are disclosed. The electronic packaging structure comprises a full panel, circuitized flexible film semiconductor chip carrier mounted on a circuitized substrate such as a printed circuit board. A plurality of semiconductor chips are mounted on the carrier in a selected pattern, and the carrier, with the chips, is mounted on a matching pattern of bonding sites on the circuitized substrate. Preferably, the circuitized flexible film semiconductor chip carrier is manufactured on a support structure used to facilitate handling of the circuitized flexible film and to facilitate heat transfer from the semiconductor chips mounted on the carrier to a heat sink which is part of the circuitized substrate. Also, the semiconductor chips mounted on the flexible film chip carrier may be tested, and burned in, while on the support structure before the chip carrier, with the chips, is mounted on the circuitized substrate.