Abstract: An inductor for an integrated circuit or integrated circuit package comprises a three-dimensional structure. In one embodiment the inductor is arranged on an integrated circuit substrate in at least two rows, each row comprising upper segments and lower segments, with the upper segments being longer than the lower segments. The upper segments in a first row are offset 180 degrees from those in an adjoining row to provide greater coupling of magnetic flux. The materials and geometry are optimized to provide a low resistance inductor for use in high performance integrated circuits. In another embodiment the inductor is arranged on an integrated circuit package substrate. Also described are methods of fabricating the inductor on an integrated circuit or as part of an integrated circuit package.

Abstract: One or more electrical characteristics of an integrated circuit device are measured at one or more relatively lower frequencies. One or more parameters of the integrated circuit device are measured at one or more frequencies higher than the one or more relatively lower frequencies. One or more parameters of the integrated circuit device are calculated based on the measured one or more electrical characteristics. The integrated circuit device is characterized based on the calculated one or more parameters and the measured one or more parameters.

Abstract: One or more electrical characteristics of an integrated circuit device are measured at one or more relatively lower frequencies. One or more parameters of the integrated circuit device are measured at one or more frequencies higher than the one or more relatively lower frequencies. One or more parameters of the integrated circuit device are calculated based on the measured one or more electrical characteristics. The integrated circuit device is characterized based on the calculated one or more parameters and the measured one or more parameters.

Abstract: An interconnection of an aluminum-copper-Group IVA metal alloy.

Abstract: A transformer comprises a substrate comprising a semiconductor material, a first conductor over the substrate, a second conductor over the substrate, and a magnetic layer over the substrate. The first conductor defines a generally spiral-shaped signal path having at least one turn. The second conductor defines a generally spiral-shaped signal path having at least one turn.

Abstract: A transformer comprises a first inductor and a second inductor. The first inductor has one or more trenches and comprises a first conductor defining a signal path along the one or more trenches of the first inductor. The second inductor has one or more trenches and comprises a second conductor defining a signal path along the one or more trenches of the second inductor.

Abstract: A dielectric layer is formed over a substrate comprising a semiconductor material. A magnetic layer is formed over the dielectric layer. The magnetic layer comprises an amorphous alloy comprising cobalt.

Abstract: An inductor comprises a substrate comprising a semiconductor material, a first dielectric layer over the substrate, a magnetic layer over the first dielectric layer, a second dielectric layer over the magnetic layer, and a conductor over the second dielectric layer.

Abstract: Novel metal-alloy interconnections for integrated circuits. The metalalloy interconnections of the present invention comprise a substantial portion of either copper or silver alloyed with a small amount of an additive having a low residual resistivity and solid solubility in either silver or copper such that the resultant electrical resistivity is less than 3&mgr;&OHgr;-cm.

Abstract: A process for fabricating embedded ground plane and shielding structures using sidewall insulators in high frequency circuits having vias or contacts. A conductive ground plane disposed between two dielectric layers has vias formed in it by removing insulating dielectric and conductive ground plane material according to a single photo-lithography masking operation. A sidewall insulator formed on vertical sidewalls of the vias, eletrically isolates the ground plane from interconnect metal passing from a lower interconnect layer to an upper interconnect layer through the vias. Alternatively, shielding structures incorporating multiple sidewall insulators and upper and lower shielding may be fabricated to entirely encapsulate the lower interconnect metal from external environments. Process efficiency and yield are increased due to the simplified processing of the embedded ground plane and shielding structures.

Abstract: Novel metal-alloy interconnections for integrated circuits. The metal-alloy interconnections of the present invention comprise a substantial portion of either copper or silver alloyed with a small amount of an additive having a low residual resistivity and solid solubility in either silver or copper such that the resultant electrical resistivity is less than 3 .mu..OMEGA.-cm.

Abstract: Features, e.g., vias or lines, are formed of copper by using selective PVD growth. A patterned structure is formed having a underlayer of a material that will accumulate copper by sputtering. An overlayer resputters the copper so that it does not accumulate a layer of copper. Copper is resputtered onto the underlayer using a sputtering ion that has a higher molecular weight than the copper. Copper is used to fill the gap defining the desired feature, and to cover an overlayer. Polishing and etchback are then used to remove the resputtered thin material and remove all of the copper on the upper surface, leaving the copper feature.

Abstract: A decoupling capacitor incorporated into an integrated circuit. The capacitor is disposed over a first region of a substrate comprising electronic circuitry, and not over a second region of the substrate. The capacitor comprises a lower and an upper conductive layer separated by an interposing insulative layer. An additional insulative layer is disposed beneath the lower conductive layer while another insulative layer is disposed above the upper conductive layer, and the capacitor provides capacitance for the electronic circuitry.

Abstract: A decoupling capacitor incorporated into an integrated circuit. The capacitor is disposed over a first region of a substrate including electronic circuitry, and not over a second region of the substrate. The capacitor including a lower and an upper conductive layer separated by an interposing insulative layer. An additional insulative layer is disposed beneath the lower conductive layer while another insulative layer is disposed above the upper conductive layer, and the capacitor provides capacitance for the electronic circuitry.

Abstract: A process for fabricating embedded ground plane and shielding structures using sidewall insulators in high frequency circuits having vias or contacts. A conductive ground plane disposed between two dielectric layers has vias formed in it by removing insulating dielectric and conductive ground plane material according to a single photo-lithography masking operation. A sidewall insulator formed on vertical sidewalls of the vias, electrically isolates the ground plane from interconnect metal passing from a lower interconnect layer to an upper interconnect layer through the vias. Alternatively, shielding structures incorporating multiple sidewall insulators and upper and lower shielding may be fabricated to entirely encapsulate the lower interconnect metal from external environments. Process efficiency and yield are increased due to the simplified processing of the embedded ground plane and shielding structures.

Abstract: The present invention describes a method for forming interconnections in semiconductor device fabrication. A via (or trench) is formed on a semiconductor substrate. A metal layer is deposited over the semiconductor substrate using directional sputtering techniques. The metal layer is deposited such that the resulting metal layer has a large surface area and a high degree of curvature. The metal layer is then reflowed. During reflow, the high degree of curvature of the metal layer improves the migration of the metal layer. Thus the metal layer is distributed in a manner that rapidly and more evenly fills the via thereby forming a reliable interconnection.

Abstract: A novel, high performance, high reliability interconnection structure for an integrated circuit. The interconnection structure of the present invention is formed on a first insulating layer which in turn is formed on a silicon substrate or well. A first multilayer interconnection comprising a first aluminum layer, a first refractory metal layer, and a second aluminum layer is formed on the first insulating layer. A second insulating layer is formed over the first multilayer interconnection. A conductive via is formed through the second insulating layer and recessed into the first multilayer interconnection wherein a portion of the via extends above the second insulating layer. A second interconnection is formed on the second insulating layer and on and around the portion of the via extending above the second insulating layer.

Abstract: A method of forming a barrier layer for preventing the diffusion of a metal interconnect through an interlayer dielectric of an integrated circuit and to act as an etch stop. A thin metal layer is formed on the interlayer dielectric and then oxidized to form a metal-oxide barrier layer.

Abstract: Novel metal-alloy interconnections for integrated circuits. The metal-alloy interconnections of the present invention comprise a substantial portion of either copper or silver alloyed with a small amount of an additive having a low residual resistivity and solid solubility in either silver or copper such that the resultant electrical resistivity is less than 3 .mu..OMEGA.-cm.

Abstract: Layered structures (e.g., Al-Si/Ti/Al-Si . . . ) and homogeneous alloys of aluminum and aluminum/1 at. % silicon with titanium and tungsten and other refractory metals have been found to significantly reduce hillock densities in the films when small amounts of titanium or tungsten are homogeneously added. However, the resistivity of the films can become excessive. In addition, a new type of low density hillock can form. Layering of the films eliminates all hillocks and results in films of low resistivity. Such layered and homogeneous films made with Al-Si and Ti were found to be dry etchable. Electrical shorts in test structures with two levels of metal and LPCVD SiO2 as an interlayer dielectric have been characterized and layered films using Al-Si and Ti gave excellent results.