Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a magnetic material on a substrate, wherein the magnetic material comprises rhenium, cobalt, iron and phosphorus, and annealing the magnetic material at a temperature below about 330 degrees Celsius, wherein the coercivity of the annealed magnetic material is below about 1 Oersted.

Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of magnetic material and at least one via structure disposed in a first dielectric layer, forming a second dielectric layer disposed on the first magnetic layer, forming at least one conductive structure disposed in the second dielectric layer, forming a third layer of dielectric material disposed on the conductive structure, forming a second layer of magnetic material disposed in the third layer of dielectric material and in the second layer of dielectric material, wherein the first and second layers of the magnetic material are coupled to one another.

Abstract: A laser driver for high speed interconnections may convert a digital signal to a current train of a bias mode to represent logical zero and of a modulation mode to represent logical one. An optical signal thus produced may include an optical offset. An optical receiver may include a photo-detector to receive the optical signal and generate a current signal, which includes a corresponding current offset. A first amplifier stage converts the current signal to a voltage signal and a second amplifier stage generates a digital output from the voltage signal. One or more low-pass filters may be used to filter the digital output and generate a filtered offset signal for a differential amplifier to generate an offset cancellation signal. The offset cancellation signal may be provided to offset cancellation circuitry to remove the current offset from the current signal generated by the photo-detector.

Abstract: An embodiment is an inductor that may include a slotted magnetic material to decrease eddy currents therein that may limit the operation of the inductor at high frequency. An embodiment may employ electro- or electroless plating techniques to form a layer or layers of magnetic material within the slotted magnetic material structure, and in particular those magnetic material layers adjacent to insulator layers.

Abstract: A transformer comprises a substrate comprising a semiconductor material, a first conductor over the substrate, a second conductor over the substrate, and a magnetic layer over the substrate. The first conductor defines a generally spiral-shaped signal path having at least one turn. The second conductor defines a generally spiral-shaped signal path having at least one turn.

Abstract: An embodiment is a magnetic via. More specifically, an embodiment is a magnetic via that increases the inductance of, for example, an integrated inductor or transformer while mitigating eddy currents therein that may limit the operation of the inductor or transformer at high frequency.

Abstract: A transformer comprises a substrate comprising a semiconductor material, a first conductor over the substrate, a second conductor over the substrate, and a magnetic layer over the substrate. The first conductor defines a generally spiral-shaped signal path having at least one turn. The second conductor defines a generally spiral-shaped signal path having at least one turn.

Abstract: An embodiment is a magnetic via. More specifically, an embodiment is a magnetic via that increases the inductance of, for example, an integrated inductor or transformer while mitigating eddy currents therein that may limit the operation of the inductor or transformer at high frequency.

Abstract: In accordance with some embodiments, a pulse width modulator having a comparator with an applied adjustable waveform to generate a bit stream with a controllably adjustable duty cycle is provided.

Abstract: A dielectric layer is formed over a substrate comprising a semiconductor material. A magnetic layer is formed over the dielectric layer. The magnetic layer comprises an amorphous alloy comprising cobalt.

Abstract: An inductor for an integrated circuit or integrated circuit package comprises a three-dimensional structure. In one embodiment the inductor is arranged on an integrated circuit substrate in at least two rows, each row comprising upper segments and lower segments, with the upper segments being longer than the lower segments. The upper segments in a first row are offset 180 degrees from those in an adjoining row to provide greater coupling of magnetic flux. The materials and geometry are optimized to provide a low resistance inductor for use in high performance integrated circuits. In another embodiment the inductor is arranged on an integrated circuit package substrate. Also described are methods of fabricating the inductor on an integrated circuit or as part of an integrated circuit package.

Abstract: An embodiment is an inductor that may include a slotted magnetic material to decrease eddy currents therein that may limit the operation of the inductor at high frequency. An embodiment may employ electro- or electroless plating techniques to form a layer or layers of magnetic material within the slotted magnetic material structure, and in particular those magnetic material layers adjacent to insulator layers.

Abstract: Multiple-inductor embodiments for use in substrates are provided herein.

Abstract: An embodiment is a magnetic via. More specifically, an embodiment is a magnetic via that increases the inductance of, for example, an integrated inductor or transformer while mitigating eddy currents therein that may limit the operation of the inductor or transformer at high frequency.

Abstract: An embodiment is a magnetic via. More specifically, an embodiment is a magnetic via that increases the inductance of, for example, an integrated inductor or transformer while mitigating eddy currents therein that may limit the operation of the inductor or transformer at high frequency.

Abstract: An embodiment is an inductor that may include a laminated material structure to decrease eddy currents therein that may limit the operation of the inductor at high frequency. An embodiment may employ electroless plating techniques to form a layer or layers of magnetic material within the laminated material structure, and in particular those magnetic layers adjacent to insulator layers.

Abstract: An inductor and multiple inductors embedded in a substrate (e.g., IC package substrate, board substrate, and/or other substrate) is provided herein.

Abstract: A method and apparatus for multi-phase transformers are described. In one embodiment, a coupled inductor topology for the multi-phase transformers comprising N primary inductors. In one embodiment, each primary inductor is coupled to one of N input nodes and a common output node. The transformer further includes N?1 secondary inductors coupled in series between one input node and the common output node. In one embodiment, the N?1 secondary inductors are arranged to couple energy from N?1 of the primary inductors to provide a common node voltage as an average of N input node voltages, wherein N is an integer greater than two. Other embodiments are described and claimed.

Abstract: An inductor comprises a substrate comprising a semiconductor material, a first dielectric layer over the substrate, a magnetic layer over the first dielectric layer, a second dielectric layer over the magnetic layer, and a conductor over the second dielectric layer.

Abstract: The optical modulator may include a strained layer of SiGe to confine carriers in a quantum well. The strained layer of SiGe may be doped with arsenic to provide electrons. The optical modulator may receive an optical signal and modulate the received signal by altering the absorption coefficient of the strained layer of SiGe responsive to an electrical signal. The optical modulator device device may be suitable for use in chip-to-chip and on-chip interconnections.