Abstract: A semiconductor memory circuit enabling replacement of defective memory elements and associated circuitry with non-defective spare elements of the RAM and associated circuitry, is scanned to enable replacement of a defective RAM element prior to repair of the RAM. A set of set/reset latches are coupled to receive the signal from the memory elements, and a multiplexer control circuit coupled to receive a shift signal and a ram_inhibit signal from a multiplexer to provide specific input signals to the multiplexer components. When a scan operation begins an active clock signal sets a set/reset latch to ram_inhibit mode and this blocks the memory elements from influencing the state of memory output latches, whereby when an memory operation begins, an active clocking signal will reset the set/reset latch into system mode to cause the multiplexers pass appropriate signals from the memory elements to the output latches, and the spare memory element is activated to replace a defective memory element.

Abstract: A system for generating one or more common address signals for multi-port memory arrays. The system includes circuitry receiving one or more read address signal; circuitry receiving one or more write address signal; circuitry receiving an array clock signal; circuitry receiving one or more enable signal; and circuitry generating the common address signals in response to the enable signal, the array clock signal and one of the read address signal and write address signal.

Abstract: A method and apparatus for providing flexible modular redundancy allocation for memory built in self test of random access memory with redundancy. The apparatus includes a first redundancy support register that includes inputs for receiving an address of a location in memory under test and data relating to must fix repair elements. The address includes a row and column vector of the location. The first redundancy support register also includes outputs for transmitting the address and data. The apparatus also includes a second redundancy support register including inputs for receiving the address and data from the outputs of the first redundancy support register. Each of the inputs of the second redundancy support register shares a one-to-one correspondence to each of the outputs of the first redundancy support register. The apparatus further includes allocation logic for providing a modular implementation of the first redundancy support register and the second redundancy support register.

Abstract: A decoder circuit includes a pulse powered stage having a plurality of fan-in inputs thereto, a dynamic stage fed by the pulse powered stage, and a replica node selectively coupled to an output node of the pulse powered stage by a pass device. The pass device and the dynamic stage are controlled by a clock signal so as to enable a self-timed evaluation of the pulse-powered stage with a clocked enablement of the dynamic stage.

Abstract: A semiconductor memory circuit enabling replacement of defective memory elements and associated circuitry with non-defective spare elements of the RAM and associated circuitry, is scanned to enable replacement of a defective RAM element prior to repair of the RAM. A set of set/reset latches are coupled to receive the signal from the memory elements, and a multiplexer control circuit coupled to receive a shift signal and a ram_inhibit signal from a multiplexer to provide specific input signals to the multiplexer components. When a scan operation begins an active clock signal sets a set/reset latch to ram_inhibit mode and this blocks the memory elements from influencing the state of memory output latches, whereby when an memory operation begins, an active clocking signal will reset the set/reset latch into system mode to cause the multiplexers pass appropriate signals from the memory elements to the output latches, and the spare memory element is activated to replace a defective memory element.

Abstract: A CMOS static random access memory (SRAM) cell array, an integrated chip including the array and a method of accessing cells in the array with improved cell stability. Bit lines connected to half selected cells in the array are floated during cell accesses for improved cell stability.

Abstract: A decoder circuit includes a pulse powered stage having a plurality of fan-in inputs thereto, a dynamic stage fed by the pulse powered stage, and a replica node selectively coupled to an output node of the pulse powered stage by a pass device. The pass device and the dynamic stage are controlled by a clock signal so as to enable a self-timed evaluation of the pulse-powered stage with a clocked enablement of the dynamic stage. A pull up device restores the dynamic stage to a precharged condition, the pull up device controlled by a second clock signal independent of the first clock signal.

Abstract: The invention may comprise circuit for programmable control of a discharge deactivation signal when interfacing local bitlines to a global bitline or other circuit. The invention may also comprise a method for programmable ground circuit control for control of a discharge signal deactivation when interfacing local bitlines to a global bitline via a bitline evaluation discharge device comprising: providing input logic states to inputs of a controller circuit; outputting an adjustable ground value from the controller circuit; and controlling the bitline evaluation discharge device with the adjustable ground value.

Abstract: A circuit and a method for writing a binary value to a memory cell are provided. The circuit includes a first field-effect transistor having a first drain, a first drain, and a first gate operably coupled between the first drain and the first source. The first drain is operably coupled to a first memory cell. The first gate configured to receive a first data signal. The circuit further includes a second field-effect transistor having a second drain, a second source, and a second gate operably coupled between the second drain and the second source. The drain source is operably coupled to the first memory cell. The second gate is configured to receive a second data signal. The circuit further includes a first signal inverter having a first input terminal and a first output terminal. The first output terminal is operably coupled to both of the first and second sources.

Abstract: A bitline selection apparatus for a semiconductor memory device includes a first local bitline pair and a second local bitline pair selectively coupled to a global bitline pair, each of the first and second local bitline pairs including a true bitline and a complementary bitline. Each of the true bitlines is selectively coupled to a common true node through an n-type pass device and a p-type pass device in parallel therewith, and each of the complementary bitlines is selectively coupled to a common complementary node through an n-type pass device and a p-type pass device in parallel therewith.

Abstract: A global and local read control synchronization method and system are provided for a memory array configured with multiple memory subarrays. Address signals are decoded to activate based thereon subarray select signals and a cumulative subarray select signal. The cumulative subarray select signal goes active whenever a subarray select signal goes active, and therefore, each pulse of the cumulative subarray select signal is synchronous with one pulse of the subarray select signals. Local read control signals for the multiple memory subarrays are obtained employing the subarray select signals, and at least one global read control signal for the memory array is obtained employing the cumulative subarray select signal. In one example, the memory array has a hierarchical bitline architecture.

Abstract: Embodiments of the invention include a circuit for interfacing local bitlines to a global bitline. The circuit includes an interface line coupled to a local bitline through a local bitline device. A global output device has an input coupled to the interface line and an output coupled to the global bitline. A clamping device is coupled to the interface line, the clamping device coupling the interface line to ground in response to a data in signal. A memory having the circuit is also disclosed.

Abstract: An output timing control circuit for use with a memory array. The output timing control circuit includes a redundancy decode circuit and a bit column output circuit. The bit column output circuit includes a first bit column output gate and a second bit column output gate, each bit column output gate is coupled to a bitline in the memory array. A precharge circuit is coupled to an output of the first bit column output gate and the second bit column output gate. The precharge circuit is responsive to a port enable signal. The redundancy decode circuit receives the port enable signal and a fuse signal and activates one of the first bit column output gate and the second bit column output gate.

Abstract: A memory redundancy control apparatus includes a static compare stage configured to compare bits of a requested memory address to corresponding fuse information bits representing a defective memory address. A dynamic stage is configured to receive outputs of the static compare stage, with an output of the dynamic stage being precharged so as to initially deactivate primary subarray decoding circuitry. The dynamic stage is further triggered by a clock signal thereto. Upon activation of the clock signal, the output of the dynamic stage remains precharged whenever a match exists between the requested memory address and the defective memory address, and the output of the dynamic stage is discharged whenever a mismatch exists between the requested memory address and the defective memory address.

Abstract: An apparatus for implementing multiple memory column redundancy within an individual memory array includes a plurality of memory array elements internally partitioned into at least a pair of subcolumn elements. At least one spare memory element is configured at a size corresponding to one of the subcolumn elements. An input redundancy multiplexing stage and an output redundancy multiplexing stage are configured for steering around one or more defective memory array elements, and an input bit decoding stage and an output bit decoding stage are configured for implementing an additional, external multiplexing stage with respect to the input redundancy multiplexing stage and the output redundancy multiplexing stage.

Abstract: A method of generating access signals for a memory array. The method includes receiving a synchronization signal and generating a wordline select signal in response to the synchronization signal. A local precharge signal is generated in response to the synchronization signal. A precharge signal is generated in response to the synchronization signal, the precharge signal being a row signal for regulating memory array read operations. A write signal is generated in response to the synchronization signal, the write signal being a row signal for regulating memory array write operations.

Abstract: The method described uses a Skip-Over technique which requires a set of muxes at the input and output of a block that is to be repaired. The improved method of implementing I/O redundancy control logic has a minimal impact to both chip area and chip wire tracks. To overcome problems of required real estate usage on a chip that was undesirable enables use of odd and even decoder outputs that can share a single wire track, the same wire being utilizable for both odd and even decoder outputs. In order to implement the decode and carry function as a centralized function, there arises a requirement that logically adjacent decode circuits (decoders connected by a carry signal) should be physically close together to minimize the overhead of the carry wiring. If the decode structure and the mux structure are arranged orthogonal to each other, then each decoder output would require a wire track. The described method however, allows odd and even decoder outputs to share the same wire track.

Abstract: A high speed latch and compare function providing rapid cache comparison through the use of a dual rail comparison circuit having transmission gate exclusive or (XOR) circuits.

Abstract: A high speed latch and compare function providing rapid cache comparison through the use of a dual rail comparison circuit having transmission gate exclusive or (XOR) circuits.

Abstract: ABIST apparatus with integrated directory compare logic functionality, and ABIST error detection functionality. The apparatus includes two subsystems NOR'ed together. The first subsystem is for bit-wise logically ANDing corresponding array valid bits and tag valid inputs, generating “0” for a match and “1” for a mis-match, and logically ORing the bit-wise result to generate a “1” hit if there are any bit-wise mismatches. The second subsystem further receives ABIST control logic as an input to either: (a). combine array valid bits tag valid inputs to produce valid output, or (b) compare array valid bits with tag valid inputs. The apparatus further includes logical NOR functionality for the outputs of the first and second subsystems.