Abstract: A storage device includes a data storage having first and second storage areas corresponding to different physical addresses. First data are stored in the first storage area. The storage device further includes a first memory that stores a reference count associated with the first data, and a controller that rearranges the first data from the first storage area to the second storage area in response to a change in the reference count of the first data.

Abstract: The present invention relates to a beef-specific age determination marker containing the p21 protein, to a beef-specific age determination kit containing an antibody which is specifically bound to the p21 protein, and to a method which involves detecting the p21 protein through an antigen-antibody binding reaction using an antibody which is specifically bound to the p21 protein serving as a beef-specific age determination marker in the muscle tissue of beef, so as to determine the age of the beef. According to the present invention, the p21 protein is significantly greatly expressed in the muscle tissue of beef, the age of which is lower than 30 months, and is hardly expressed in the muscle tissue of beef, the age of which is greater than 30 months, and thus can be valuably used as a beef-specific age determination marker.

Abstract: An error correction device is provided. The error correction device includes a code storage unit where a plurality of error correction codes are stored, a first error correction unit to correct a data error detected from input data by using one of a plurality of error correction codes and to output correction data, a buffer to store the correction data, and a second error correction unit to generate a new correction code from the correction data, to compare another of a plurality of error correction codes with the new correction code and to output a comparison result.

Abstract: Integrated circuit systems include a non-volatile memory device (e.g, flash EEPROM device) and a memory processing circuit. The memory processing circuit is electrically coupled to the non-volatile memory device. The memory processing circuit is configured to reallocate addressable space within the non-volatile memory device. This reallocation is performed by increasing a number of physical addresses within the non-volatile memory device that are reserved as redundant memory addresses, in response to a capacity adjust command received by the memory processing circuit.

Abstract: A data retention method that includes sampling a plurality of nonvolatile memory devices included in a data storage device to detect retention information for each of the nonvolatile memory devices in response to a request of a host and outputting, from the data storage device to the host, sampling data based on a result of the sampling, determining, at the host, whether to perform a retention operation on each of the nonvolatile memory devices based on the sampling data, and performing the retention operation on each of the nonvolatile memory devices based on a result of the determination.

Abstract: A method and apparatus to interface a semiconductor storage device and a host in order to provide performance throttling of the semiconductor storage device. In the method, the semiconductor storage can receive a setting request command from the host. The semiconductor storage device sets a performance throttling parameter to a particular value in response to the setting request command. The semiconductor storage device can send to the host a setting response signal indicating completion of the setting of the performance throttling parameter.

Abstract: A semiconductor storage device and a method of throttling performance of the same are provided. The semiconductor storage device includes a non-volatile memory device configured to store data in a non-volatile state; and a controller configured to control the non-volatile memory device. The controller calculates a new performance level, compares the calculated performance level with a predetermined reference, and determines the calculated performance level as an updated performance level according to the comparison result.

Abstract: A semiconductor storage device (SSD) and a method of throttling performance of the SSD. The method can include gathering at least two workload data items related with a workload of the semiconductor storage device, estimating the workload using the at least two workload data items, and throttling the performance of the semiconductor storage device according to the estimated workload. Accordingly, a workload that the semiconductor storage device will undergo can be estimated.

Abstract: A semiconductor storage device and a method of throttling performance of the same are provided. The semiconductor storage device includes a non-volatile memory device; and a controller configured to receive a write command from a host and program write data received from the host to the non-volatile memory device in response to the write command. The controller inserts idle time after receiving the write data from the host and/or after programming the write data to the non-volatile memory device.

Abstract: Integrated circuit systems include a non-volatile memory device (e.g, flash EEPROM device) and a memory processing circuit. The memory processing circuit is electrically coupled to the non-volatile memory device. The memory processing circuit is configured to reallocate addressable space within the non-volatile memory device. This reallocation is performed by increasing a number of physical addresses within the non-volatile memory device that are reserved as redundant memory addresses, in response to a capacity adjust command received by the memory processing circuit.

Abstract: Integrated circuit systems include a non-volatile memory device (e.g, flash EEPROM device) and a memory processing circuit. The memory processing circuit is electrically coupled to the non-volatile memory device. The memory processing circuit is configured to reallocate addressable space within the non-volatile memory device. This reallocation is performed by increasing a number of physical addresses within the non-volatile memory device that are reserved as redundant memory addresses, in response to a capacity adjust command received by the memory processing circuit.

Abstract: A data storage system includes a non-volatile memory, a disc recording medium, a non-volatile memory buffer, operatively disposed between a host interface and the non-volatile memory, which stores a portion of data stored in the non-volatile memory, and a disc buffer, operatively disposed between the host interface and the disc recording medium, which stores a portion of data stored in the disc recording medium. The data storage system may be configured to receive an access address from a host operatively connected to the host interface, and sequentially determine whether the access address exists in one of the non-volatile memory buffer, the non-volatile memory, the disc buffer, and the disc recording medium, in that order.

Abstract: A data storage system includes a non-volatile memory, a disc recording medium, a non-volatile memory buffer, operatively disposed between a host interface and the non-volatile memory, which stores a portion of data stored in the non-volatile memory, and a disc buffer, operatively disposed between the host interface and the disc recording medium, which stores a portion of data stored in the disc recording medium. The data storage system may be configured to receive an access address from a host operatively connected to the host interface, and sequentially determine whether the access address exists in one of the non-volatile memory buffer, the non-volatile memory, the disc buffer, and the disc recording medium, in that order.

Abstract: A data storage system includes a non-volatile memory, a disc recording medium, a non-volatile memory buffer, operatively disposed between a host interface and the non-volatile memory, which stores a portion of data stored in the non-volatile memory, and a disc buffer, operatively disposed between the host interface and the disc recording medium, which stores a portion of data stored in the disc recording medium. The data storage system may be configured to receive an access address from a host operatively connected to the host interface, and sequentially determine whether the access address exists in one of the non-volatile memory buffer, the non-volatile memory, the disc buffer, and the disc recording medium, in that order.

Abstract: An error correction device is provided. The error correction device includes a code storage unit where a plurality of error correction codes are stored, a first error correction unit to correct a data error detected from input data by using one of a plurality of error correction codes and to output correction data, a buffer to store the correction data, and a second error correction unit to generate a new correction code from the correction data, to compare another of a plurality of error correction codes with the new correction code and to output a comparison result.

Abstract: A non-volatile memory may include a plurality of map blocks for storing a plurality of map units, the map units representing mapping information between physical addresses and logical addresses. A storage device may include such a non-volatile memory. A method of mapping such a non-volatile memory may include writing historical information regarding locations of valid map units among the map units included in map blocks previously allocated among the map blocks when a new map block among the map blocks is allocated, the valid map units representing valid mapping information, and constructing a map table including all of the valid mapping information based on the historical information and a result of searching a map block recently allocated among the map blocks.

Abstract: A data storage system includes a non-volatile memory, a disc recording medium, a non-volatile memory buffer, operatively disposed between a host interface and the non-volatile memory, which stores a portion of data stored in the non-volatile memory, and a disc buffer, operatively disposed between the host interface and the disc recording medium, which stores a portion of data stored in the disc recording medium. The data storage system may be configured to receive an access address from a host operatively connected to the host interface, and sequentially determine whether the access address exists in one of the non-volatile memory buffer, the non-volatile memory, the disc buffer, and the disc recording medium, in that order.

Abstract: A memory card capable of having an increased number of meta blocks and a method of driving the memory card. A method of reading data from the memory card includes receiving logical addresses from a host. It is determined whether memory blocks corresponding to the received logical addresses belong to a first region allocated to a user data region in the memory card or a second region including meta blocks in the memory card. The memory blocks corresponding to the logical addresses are masked as erased blocks when the memory blocks belong to the second region.

Abstract: Integrated circuit systems include a non-volatile memory device (e.g, flash EEPROM device) and a memory processing circuit. The memory processing circuit is electrically coupled to the non-volatile memory device. The memory processing circuit is configured to reallocate addressable space within the non-volatile memory device. This reallocation is performed by increasing a number of physical addresses within the non-volatile memory device that are reserved as redundant memory addresses, in response to a capacity adjust command received by the memory processing circuit.

Abstract: A flash memory includes an array of memory cells having sources, drains, floating gates, and control gates. The array includes a conductive plate formed over the memory cells to affect a capacitive coupling between the memory cells and the conductive plate. A first voltage source provides a first voltage to the control gate of a selected one of the memory cells. A second voltage source provides a second voltage to the conductive plate after the control gate of the selected one of the memory cells has been charged up to a predetermined voltage level. Additionally, the flash memory includes a switching circuit to transfer the first and second voltages to the control gate of the selected memory cell and the conductive plate, respectively, responsive to a first and second control signals.