Patents by Inventor Dong Gun Kim

Dong Gun Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11182245
    Abstract: An operating method of a memory controller to update metadata using journaling data in a short time during a booting operation, and to maintain reliability of the updated metadata. The operating method of a memory controller includes loading metadata into sub-regions of a buffer memory, updating the metadata using journaling data in a state that error correction code (ECC) functions of memory controller for the sub-regions are disabled, generating a first parity data of data stored in the first sub-region, and enabling the ECC function of the first sub-region, after the first parity data is generated.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: November 23, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bo Mi Kim, Dong Gun Kim, Soo Hyun Kim, Ki Hyun Choi, Pil Chang Son
  • Patent number: 11113149
    Abstract: A method of operating a storage device includes receiving a first logical address from a host, determining whether first metadata stored in a volatile memory of the storage device and associated with the first logical address is corrupted, processing the first metadata as an uncorrectable error when the first metadata is determined to be corrupted, providing an error message to the host indicating that an operation cannot be performed on data associated with the first logical address when the first metadata is processed as the uncorrectable error, after the providing of the error message, receiving a second logical address from the host, determining whether second metadata stored in the volatile memory and associated with the second logical address is corrupted, and performing an operation of accessing the non-volatile memory based on the second metadata, when the second metadata is not determined to be corrupted.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: September 7, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Won Kim, Dong-Young Seo, Dong-Gun Kim
  • Patent number: 11102687
    Abstract: Disclosed is a 5G or a pre-5G communication system provided to support a higher data transmission rate than a system after a 4G communication system such as LTE.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: August 24, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong Gun Kim, Seung Ri Jin, Soeng Hun Kim, Alexander Sayenko
  • Publication number: 20210259036
    Abstract: Methods and apparatuses are provided in a wireless communication system in which a radio resource control (RRC) message is received to change or release a secondary cell group (SCG). A re-establishment for a radio link control (RLC) entity of a terminal is performed based on the RRC message. A packet data convergence protocol (PDCP) data recovery is performed based on the RRC message. Performing the PDCP data recovery includes selectively transmitting a PDCP protocol data unit (PDU) previously submitted to the re-established RLC entity, for which a successful delivery has not been confirmed by the re-established RLC entity.
    Type: Application
    Filed: May 3, 2021
    Publication date: August 19, 2021
    Inventor: Dong Gun KIM
  • Publication number: 20210259037
    Abstract: A method, performed by a user equipment (UE), of transmitting and receiving signals in a wireless communication system, according to an embodiment, includes receiving a logical channel release request from a next-generation node B (gNB), determining a logical channel to release, an operation mode of the logical channel to release, and whether a packet data convergence protocol (PDCP) layer apparatus connected to the logical channel is re-established, based on the logical channel release request, and performing PDCP data recovery based on the determination result.
    Type: Application
    Filed: May 3, 2021
    Publication date: August 19, 2021
    Inventors: Dong gun KIM, Sang Bum KIM, Soeng Hun KIM, Alexander SAYENKO, Jae Hyuk JANG, Seung Ri JIN
  • Patent number: 11087826
    Abstract: Provided is a method including acquiring reading and writing information of logical chunks of a storage apparatus in a number of historical periods before a current time, and predicting reading and writing information of the logical chunks in a next period according to reading and writing information of the logical chunks in a number of historical periods before the current time and a data prediction model. The data prediction model indicates a relationship between reading and writing information of the logical chunks in a next period and reading and writing information of the logical chunks in a number of historical periods before the current time.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: August 10, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Pan Yang, Dong-gun Kim, Wei Xia
  • Publication number: 20210176661
    Abstract: Provided is a method, performed by a user equipment (UE), of processing data in a wireless communication system, the method including: determining a format for buffer status report based on a buffer status of each of logical channel groups when the UE receiving an uplink transmission resource from a base station determines to report the buffer status to the base station; allocating, to each of the logical channel groups, a transmission resource remaining after excluding, from the uplink transmission resource, a transmission resource used for reporting the buffer status of the determined format; and re-determining the format for the buffer status report based on the buffer status of each of the logical channel groups after the allocating.
    Type: Application
    Filed: November 8, 2018
    Publication date: June 10, 2021
    Inventor: Dong Gun KIM
  • Publication number: 20210144062
    Abstract: A method of UE includes receiving a radio resource control (RRC) message for configuring bandwidth parts (BWPs) of a serving cell, receiving a physical downlink control channel (PDCCH) indicating activation of a first BWP, performing a BWP switching to the first BWP indicated by the PDCCH, and starting a first downlink BWP timer associated with the first BWP. A UE includes a transceiver, and at least one controller coupled with the transceiver, the at least one controller configured to receive an RRC message for configuring BWPs of a serving cell, receive a PDCCH indicating activation of a first BWP, perform a BWP switching to the first BWP indicated by the PDCCH, and start a first downlink BWP timer associated with the first BWP.
    Type: Application
    Filed: January 18, 2021
    Publication date: May 13, 2021
    Inventors: Seung Ri JIN, Soeng Hun KIM, Dong Gun KIM, Jae Hyuk JANG, Alexander SAYENKO
  • Patent number: 10999884
    Abstract: Provided is a user equipment method of transmitting and receiving data in a wireless communication system, comprising receiving a request for a packet data convergence protocol (PDCP) data recovery from an upper layer, determining at least one PDCP packet data unit (PDU), previously submitted to a re-established radio link control (RLC) entity, for which a successful delivery has not been confirmed by a lower layer, and performing a retransmission of the determined at least one PDCP PDU.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: May 4, 2021
    Inventor: Dong Gun Kim
  • Patent number: 10936481
    Abstract: A semiconductor system may include: a volatile memory device that stores an address mapping table including mapping information for a non-volatile memory device; and a control device suitable for reading one or more seed values from the volatile memory device before the address mapping table is stored, generating a plurality of random values based on the seed values, and initializing mapping information to the plurality of random values.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: March 2, 2021
    Assignee: SK hynix Inc.
    Inventors: Yong-Ju Kim, Dong-Gun Kim, Do-Sun Hong
  • Publication number: 20210055988
    Abstract: An operating method of a memory controller to update metadata using journaling data in a short time during a booting operation, and to maintain reliability of the updated metadata. The operating method of a memory controller includes loading metadata into sub-regions of a buffer memory, updating the metadata using journaling data in a state that error correction code (ECC) functions of memory controller for the sub-regions are disabled, generating a first parity data of data stored in the first sub-region, and enabling the ECC function of the first sub-region, after the first parity data is generated.
    Type: Application
    Filed: April 24, 2020
    Publication date: February 25, 2021
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bo Mi KIM, Dong Gun KIM, Soo Hyun KIM, Ki Hyun CHOI, Pil Chang SON
  • Patent number: 10897399
    Abstract: A method of UE includes receiving a radio resource control (RRC) message for configuring bandwidth parts (BWPs) of a serving cell, receiving a physical downlink control channel (PDCCH) indicating activation of a first BWP, performing a BWP switching to the first BWP indicated by the PDCCH, and starting a first downlink BWP timer associated with the first BWP. A UE includes a transceiver, and at least one controller coupled with the transceiver, the at least one controller configured to receive an RRC message for configuring BWPs of a serving cell, receive a PDCCH indicating activation of a first BWP, perform a BWP switching to the first BWP indicated by the PDCCH, and start a first downlink BWP timer associated with the first BWP.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: January 19, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung Ri Jin, Soeng Hun Kim, Dong Gun Kim, Jae Hyuk Jang, Alexander Sayenko
  • Patent number: 10871919
    Abstract: A memory system may include a memory device comprising a plurality of memory banks, and a memory controller suitable for allocating data of successive logical addresses to the respective memory banks, and controlling read/write operations of the data, wherein the memory controller groups pages of the respective memory banks, and performs a wear-leveling operation based on the read/write operations of the data on each group of the pages.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: December 22, 2020
    Assignee: SK hynix Inc.
    Inventors: Do-Sun Hong, Dong-Gun Kim, Yong-Ju Kim
  • Patent number: 10846220
    Abstract: A memory system may include: a memory device having a plurality of banks, each comprising a memory cell region including a plurality of memory cells, and a page buffer unit; and a controller suitable for receiving a write address and write data from a host, and controlling a write operation of the memory device, wherein the controller comprises: a page buffer table (PBT) comprising fields to retain the same data as the page buffer units of the respective banks; and a processor suitable for comparing the write data to data stored in a field of the PBT, corresponding to the write address, and controlling the memory device to write the write data or the data stored in the page buffer unit to memory cells selected according to the write address, based on a comparison result.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: November 24, 2020
    Assignee: SK hynix Inc.
    Inventors: Seung-Gyu Jeong, Dong-Gun Kim, Do-Sun Hong
  • Publication number: 20200349089
    Abstract: A cache system includes a cache memory having a plurality of blocks, a dirty line list storing status information of a predetermined number of dirty lines among dirty lines in the plurality of blocks, and a cache controller controlling a data caching operation of the cache memory and providing statuses and variation of statuses of the dirty lines, according to the data caching operation, to the dirty line list. The cache controller performs a control operation to always store status information of a least-recently-used (LRU) dirty line into a predetermined storage location of the dirty line list.
    Type: Application
    Filed: December 12, 2019
    Publication date: November 5, 2020
    Applicant: SK hynix Inc.
    Inventors: Seung Gyu JEONG, Dong Gun KIM
  • Patent number: 10795763
    Abstract: A memory system includes a plurality of memory chips suitable for storing data and an error correction code thereof, an error correction circuit suitable for detecting and correcting error bits of data, which are read from the plurality of memory chips, based on an error correction code of the read data, an address storage circuit suitable for storing addresses of first data, among the read data, the first data having a number of detected error bits greater than or equal to a first number, and a failed chip detection circuit suitable for, when the number of the stored addresses is greater than or equal to a second number, detecting a failed memory chip where a chip-kill occurs by writing test data in the plurality of memory chips and reading back the written test data.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: October 6, 2020
    Assignee: SK hynix Inc.
    Inventors: Yong-Ju Kim, Do-Sun Hong, Dong-Gun Kim
  • Publication number: 20200260496
    Abstract: Disclosed are a communication technique for merging, with IoT technology, a 5G communication system for supporting a data transmission rate higher than that of a 4G system and a system therefor. The present disclosure can be applied to intelligent services (for example, smart home, smart building, smart city, smart car or connected car, healthcare, digital education, retail, security and safety-related services, and the like) on the basis of 5G communication technology and IoT-related technology. Disclosed is a method by which a terminal performs a random access, comprising: receiving, from a serving base station, a handover command including configuration information indicating a dedicated random access resource and a common random access resource determining whether to perform a random access by using at least one of the dedicated random access resource and the common random access resource according to predetermined criteria; and performing the random access on the basis of the determination result.
    Type: Application
    Filed: September 13, 2018
    Publication date: August 13, 2020
    Inventors: Seung-Ri JIN, Soeng-Hun KIM, Sang-Bum KIM, Dong-Gun KIM
  • Patent number: 10720278
    Abstract: A multilayer ceramic capacitor with decreased high voltage stress defects and a board having the same may include a body formed by stacking a plurality of dielectric layers and a plurality of first and second internal electrodes in a width direction, the first and second internal electrodes including body portions overlapping each other and lead portions exposed to a mounting surface of the body and disposed to be spaced apart from each other, respectively; and first to third external electrodes disposed on the mounting surface of the capacitor body to be connected to the lead portions, respectively, wherein the body portions of the first and second internal electrodes have different areas from each other.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: July 21, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Young Heon Oh, Se Hwan Bong, Young Ha Kim, Dong Gun Kim
  • Publication number: 20200225980
    Abstract: A computing system includes a host and a storage device. The host includes a central processing unit (CPU) and a first volatile memory device. The storage device includes a second volatile memory device and a nonvolatile memory device. The CPU uses the first volatile memory device and the second volatile memory device as a main memory to store temporary data used for operation of the CPU. The CPU determines a swap-out page to be swapped-out of first pages stored in the first volatile memory device, determines a swap-in page to be swapped-in of second pages stored in the second volatile memory device, and exchanges the swapped-out page and the swapped-in page.
    Type: Application
    Filed: March 23, 2020
    Publication date: July 16, 2020
    Inventors: Dong-Gun KIM, Won-Moon CHEON
  • Publication number: 20200167231
    Abstract: A method of operating a storage device includes receiving a first logical address from a host, determining whether first metadata stored in a volatile memory of the storage device and associated with the first logical address is corrupted, processing the first metadata as an uncorrectable error when the first metadata is determined to be corrupted, providing an error message to the host indicating that an operation cannot be performed on data associated with the first logical address when the first metadata is processed as the uncorrectable error, after the providing of the error message, receiving a second logical address from the host, determining whether second metadata stored in the volatile memory and associated with the second logical address is corrupted, and performing an operation of accessing the non-volatile memory based on the second metadata, when the second metadata is not determined to be corrupted.
    Type: Application
    Filed: January 16, 2020
    Publication date: May 28, 2020
    Inventors: JONG-WON KIM, Dong-Young Seo, Dong-Gun Kim