Abstract: Provided is a user equipment method of transmitting and receiving data in a wireless communication system, comprising receiving a request for a packet data convergence protocol (PDCP) data recovery from an upper layer, determining at least one PDCP packet data unit (PDU), previously submitted to a re-established radio link control (RLC) entity, for which a successful delivery has not been confirmed by a lower layer, and performing a retransmission of the determined at least one PDCP PDU.

Abstract: Provided is a method for performing uplink data compression (UDC) by a user equipment (UE). The method includes receiving configuration information on UDC; generating a first UDC packet by compressing uplink data, based on the configuration information on UDC; transmitting the first UDC packet; receiving, from the base station, packet data convergence protocol (PDCP) layer control information including checksum error information about whether a checksum error has occurred in the first UDC packet; and resetting a UDC buffer used in compressing the uplink data, based on the PDCP layer control information.

Abstract: A method, performed by a user equipment (UE), of transmitting and receiving signals in a wireless communication system, according to an embodiment, includes receiving a logical channel release request from a next-generation node B (gNB), determining a logical channel to release, an operation mode of the logical channel to release, and whether a packet data convergence protocol (PDCP) layer apparatus connected to the logical channel is re-established, based on the logical channel release request, and performing PDCP data recovery based on the determination result.

Abstract: A memory system may include: a memory device having a plurality of banks, each comprising a memory cell region including a plurality of memory cells, and a page buffer unit; and a controller suitable for receiving a write address and write data from a host, and controlling a write operation of the memory device, wherein the controller comprises: a page buffer table (PBT) comprising fields to retain the same data as the page buffer units of the respective banks; and a processor suitable for comparing the write data to data stored in a field of the PBT, corresponding to the write address, and controlling the memory device to write the write data or the data stored in the page buffer unit to memory cells selected according to the write address, based on a comparison result.

Abstract: A positive electrode material for a secondary battery and a method for manufacturing the same are provided, in which manganese fluorophosphate containing lithium or sodium can be used as an electrode material. That is, a positive electrode material for a lithium/sodium battery is provided, in which intercalation/deintercalation of sodium/lithium ions is possible due to a short lithium diffusion distance caused by nanosizing of particles. Furthermore, a positive electrode material for a lithium/sodium battery is provided, which has electrochemical activity due to an increase in electrical conductivity by effective carbon coating.

Abstract: A battery cooling system includes: a housing in which an inlet duct from which air is introduced and an outlet duct through which the air is discharged are mounted; a first battery mounted in the housing and disposed between the inlet duct and the outlet duct; and a low voltage battery disposed between the first battery and the inlet duct.

Abstract: A method for operating a memory system includes: reading a data from a memory device; detecting and correcting an error of the data; when the error of the data is equal to or greater than a threshold value, deciding an address corresponding to memory cells from which the data is read in the memory device as a rewrite-requiring address; and rewriting the data of the memory cell corresponding to the rewrite-requiring address.

Abstract: A memory system may include a memory device comprising a plurality of memory banks, and a memory controller suitable for allocating data of successive logical addresses to the respective memory banks, and controlling read/write operations of the data, wherein the memory controller groups pages of the respective memory banks, and performs a wear-leveling operation based on the read/write operations of the data on each group of the pages.

Abstract: Provided is a method for mapping a logical address to a physical address, including: identifying whether a logical address is identical to a round value; mapping the logical address to a first physical address identical to an interval value when the logical address is identical to the round value; mapping the logical address to a second physical address corresponding to a value obtained by subtracting the round value from the logical address when the logical address is different from the round value; and adjusting a mapping value of the logical address to the second physical address to a value obtained by subtracting one from the second physical address when the second physical address is less than or equal to the interval value.

Abstract: A method of operating a storage device includes receiving a first logical address from a host, determining whether first metadata stored in a volatile memory of the storage device and associated with the first logical address is corrupted, processing the first metadata as an uncorrectable error when the first metadata is determined to be corrupted, providing an error message to the host indicating that an operation cannot be performed on data associated with the first logical address when the first metadata is processed as the uncorrectable error, after the providing of the error message, receiving a second logical address from the host, determining whether second metadata stored in the volatile memory and associated with the second logical address is corrupted, and performing an operation of accessing the non-volatile memory based on the second metadata, when the second metadata is not determined to be corrupted.

Abstract: a semiconductor system may include: a volatile memory device that stores an address mapping table including mapping information for a non-volatile memory device; and a control device suitable for reading one or more seed values from the volatile memory device before the address mapping table is stored, generating a plurality of random values based on the seed values, and initializing mapping information to the plurality of random values.

Abstract: A memory system includes: a non-volatile memory device including a normal region in which Most Significant Bits (MSBs) and Least Significant Bits (LSBs) stored in memory cells are accessed simultaneously, a hot region in which MSBs stored in memory cells are accessed, and a cold region in which LSBs stored in memory cells are accessed; and a memory controller controlling the non-volatile memory device, Herein, the memory controller includes: a read/write counter that counts the number of read operations and the number of write operations that are performed for each of logical cluster to thereby produce a counting result; and a region selector that maps each logical cluster to one among the normal region, the hot region and the cold region based on the counting result to thereby produce mapping data.

Abstract: A memory system includes a wear-leveling module detecting a hot memory block among a plurality of memory blocks based on the number of times write operations are performed on each of the memory blocks, and moving data from the hot memory block to a spare memory block, a counting unit counting the number of data movement from the hot memory block to the spare memory block, on each of memory regions formed by grouping the plurality of memory blocks, and output data movement counts, a first detection unit selecting one from the plurality of memory regions based on the data movement count, and detecting a cold memory block among memory blocks included in the selected memory region, and a management unit moving data from the cold memory block to the hot memory block, and managing the cold memory block as the spare memory block.

Abstract: A memory system includes a memory device performing write operations on lines included in a memory block among a plurality of memory blocks included in the memory device; a counting unit counting a write count for each of the plurality of memory blocks, and outputting the write counts; a first wear-leveling unit performing a wear leveling operation by shifting the lines of each of the plurality of memory blocks; and a second wear-leveling unit detecting hot and cold memory blocks among the plurality of memory blocks based on the write counts, and swapping the hot memory block with the cold memory block, wherein the second wear-leveling unit selects at least one memory block among the plurality of memory blocks based on the write counts, and checks whether the write operation is performed on each of the lines included in the selected memory block.

Abstract: A battery management system for a vehicle is provided to prevent current consumption of a battery by operating a relay connected between the battery and electronic loads to prevent an over-discharge of the battery. The battery management system includes a sensing unit that is configured to measure a current and a voltage of a battery for a vehicle and a relay that is connected between the battery for the vehicle and electronic units of the vehicle. Additionally, a controller is configured to receive data from the sensing unit to turn off the relay.

Abstract: An electronic system includes a host device and a storage device. The storage device includes a first memory device that is accessed by the host device by units of a byte through a byte accessible interface and a second memory device that is accessed by the host device by units of a block through a block accessible interface. The storage device performs an internal data transfer between the first memory device and the second memory device based on an internal transfer command that is provided through the block accessible interface from the host device. The electronic system may efficiently support the access by units of a byte and the access by units of a block between the host device and the storage device by performing internal data transfer in the storage device using the internal transfer command that is modified from the existing block access command.

Abstract: A method for refreshing memory cells includes: reading data from a plurality of memory cells; and performing a write operation with a first data onto memory cells from which the first data is read among the plurality of memory cells.

Abstract: A storage system includes a storage device and a host device. The storage device includes a nonvolatile memory device having a first size and a first volatile memory device having a second size smaller than the first size and configured to operate as a cache memory with respect to the nonvolatile memory device. The first volatile memory device is configured to allow a first bus portion access to cache data stored in the first volatile memory device. The host device is configured to generate a cache table corresponding to information in the cache data stored in the first volatile memory device and configured to read the cache data stored in the first volatile memory device via the first bus portion based on the cache table.

Abstract: A memory system includes a memory device performing write operations on lines included in a memory block among a plurality of memory blocks included in the memory device; a counting unit counting a write count for each of the plurality of memory blocks, and outputting the write counts; a first wear-leveling unit performing a wear leveling operation by shifting the lines of each of the plurality of memory blocks; and a second wear-leveling unit detecting hot and cold memory blocks among the plurality of memory blocks based on the write counts, and swapping the hot memory block with the cold memory block, wherein the second wear-leveling unit selects at least one memory block among the plurality of memory blocks based on the write counts, and checks whether the write operation is performed on each of the lines included in the selected memory block.

Abstract: A computing system includes a host and a storage device. The host includes a central processing unit (CPU) and a first volatile memory device. The storage device includes a second volatile memory device and a nonvolatile memory device. The CPU uses the first volatile memory device and the second volatile memory device as a main memory to store temporary data used for operation of the CPU. The CPU determines a swap-out page to be swapped-out of first pages stored in the first volatile memory device, determines a swap-in page to be swapped-in of second pages stored in the second volatile memory device, and exchanges the swapped-out page and the swapped-in page.