Patents by Inventor Dong-Gun Park

Dong-Gun Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200243684
    Abstract: A semiconductor device includes first and second fin patterns on a substrate and extending apart from each other, a field insulating film on the substrate and surrounding parts of the first and second fin patterns, a first gate structure on the first fin pattern and intersecting the first fin pattern, a second gate structure on the second fin pattern and intersecting the second fin pattern, and a separating structure protruding from a top surface of the field insulating film and separating the first and second gate structures, the field insulating film and the separating structure including a same insulating material.
    Type: Application
    Filed: April 14, 2020
    Publication date: July 30, 2020
    Inventors: Jung Gun YOU, Dong Hyun KIM, Byoung-Gi KIM, Yun Suk NAM, Yeong Min JEON, Sung Chul PARK, Dae Won HA
  • Patent number: 10727354
    Abstract: A semiconductor device includes a substrate; a vertical channel structure including a pair of active fins extended in a first direction, perpendicular to an upper surface of the substrate, and an insulating portion interposed between the pair of active fins; an upper source/drain disposed on the vertical channel structure; a lower source/drain disposed below the vertical channel structure and on the substrate; a gate electrode disposed between the upper source/drain and the lower source/drain and surrounding the vertical channel structure; and a gate dielectric layer disposed between the gate electrode and the vertical channel structure. An interval between the gate electrode and the upper source/drain may be smaller than an interval between the gate electrode and the lower source/drain in the first direction.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: July 28, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung Il Park, Jung Gun You, Dong Hun Lee, Yun Il Lee
  • Publication number: 20200220012
    Abstract: A vFET includes a first impurity region doped with first impurities at an upper portion of the substrate. A first diffusion control pattern is formed on the first impurity region. The first diffusion control pattern is configured to control the diffusion of the first impurities. A channel extends in a vertical direction substantially orthogonal to an upper surface of the substrate. A second impurity region is doped with second impurities on the channel. A second diffusion control pattern is between the channel and the second impurity region. The second diffusion control pattern is configured to control the diffusion of the second impurities. A gate structure is adjacent to the channel.
    Type: Application
    Filed: March 12, 2020
    Publication date: July 9, 2020
    Inventors: JUNG-GUN YOU, Chang-Hee KIM, Sung-II PARK, Dong-Hun LEE
  • Patent number: 10629742
    Abstract: A semiconductor device includes first and second fin patterns on a substrate and extending apart from each other, a field insulating film on the substrate and surrounding parts of the first and second fin patterns, a first gate structure on the first fin pattern and intersecting the first fin pattern, a second gate structure on the second fin pattern and intersecting the second fin pattern, and a separating structure protruding from a top surface of the field insulating film and separating the first and second gate structures, the field insulating film and the separating structure including a same insulating material.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: April 21, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung Gun You, Dong Hyun Kim, Byoung-Gi Kim, Yun Suk Nam, Yeong Min Jeon, Sung Chul Park, Dae Won Ha
  • Patent number: 10629729
    Abstract: A vFET includes a first impurity region doped with first impurities at an upper portion of the substrate. A first diffusion control pattern is formed on the first impurity region. The first diffusion control pattern is configured to control the diffusion of the first impurities. A channel extends in a vertical direction substantially orthogonal to an upper surface of the substrate. A second impurity region is doped with second impurities on the channel. A second diffusion control pattern is between the channel and the second impurity region. The second diffusion control pattern is configured to control the diffusion of the second impurities. A gate structure is adjacent to the channel.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: April 21, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Gun You, Chang-Hee Kim, Sung-Il Park, Dong-Hun Lee
  • Publication number: 20200064322
    Abstract: An electronic device can comprise: a sensor module; and a processor for acquiring periphery state information indicating information on the outside of the electronic device and/or device state information indicating information on the inside of the electronic device, acquiring a measurement profile including information regarding target gas to be measured and a detection period of the target gas on the basis of the periphery state information and/or the device state information, and detecting the target gas through the sensor module according to the measurement profile.
    Type: Application
    Filed: February 1, 2018
    Publication date: February 27, 2020
    Inventors: Hyun-Cheol PARK, Dong-Wook KIM, Sang II PARK, Sung-Gun BAE, Ik-Joo BYUN, Tae-Han LEE, Tae-Han JEON, Tae-Ho KIM, Jeong-Min PARK, Seung-Eun LEE
  • Patent number: 10534900
    Abstract: A method for providing a service by an electronic device according to various embodiments may comprise the steps of: obtaining biometric information of a user; determining at least one service associated with the biometric information out of a plurality of services that the electronic device supports; and providing the determined at least one service.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: January 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Cheol-Ho Cheong, Hyuk Kang, Dong-Hyun Kim, Yang-Su Kim, Hyun-Soo Kim, Bo-Yeon Na, Byoung-Tack Roh, Jeong-Min Park, Ji-Hyun Park, Tae-Gun Park, Kwang-Sub Son, Dong-Il Son, Sung-Ho Son, Sung-Hyuk Shin, Hyun-Seok Shin, Jin-gil Yang, Jae-Yung Yeo, Jae-Bong Yoo, Su-Ha Yoon, Seung-Young Jeon, Kyung-Soo Lim, Eui-Chang Jung, In-Ji Jin, Jong-Ho Choi, Duk-Ki Hong, Moo-Hyun Baek, Sang-Youp Seok, Byoung-Uk Yoon
  • Patent number: 10497804
    Abstract: A vertical transistor structure includes a first transistor and a second transistor. The first transistor includes a first lower electrode connected to a second upper electrode of the second transistor, and a second upper electrode connected to a first lower electrode of the second transistor. The first transistor also includes a gate electrode connected to a gate electrode of the second transistor.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: December 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Il Park, Beom-Jin Park, Yun-Il Lee, Jung-Gun You, Dong-Hun Lee
  • Patent number: 10483399
    Abstract: An integrated circuit (IC) device includes a pair of fin-shaped active areas that are adjacent to each other with a fin separation area therebetween, the pair of fin-shaped active areas extend in a line, and a fin separation insulating structure in the fin separation area, wherein the pair of fin-shaped active areas includes a first fin-shaped active area having a first corner defining part of the fin separation area, and wherein the fin separation insulating structure includes a lower insulating pattern that covers sidewalls of the pair of fin-shaped active areas, and an upper insulating pattern on the lower insulating pattern to cover at least part of the first corner, the upper insulating pattern having a top surface at a level higher than a top surface of each of the pair of fin-shaped active areas.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: November 19, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-yup Chung, Myung-yoon Um, Dong-ho Cha, Jung-gun You, Gi-gwan Park
  • Publication number: 20190328808
    Abstract: The present invention relates to a pharmaceutical composition comprising a maple leaf extract or fraction thereof for preventing or treating a retinal disease, a method for preventing or treating a retinal disease using the pharmaceutical composition, and a food composition comprising a maple leaf extract or fraction thereof for ameliorating the symptoms of a retinal disease. The pharmaceutical composition according to the present invention, which is effective for the treatment of a retinal disease, can be used pharmaceutically as a composition for preventing or treating a retinal disease, and can also be used advantageously as a health functional food.
    Type: Application
    Filed: August 11, 2017
    Publication date: October 31, 2019
    Inventors: Jin Yeul MA, Kwang Il PARK, Yeoun-Hee KIM, Tae Woo OH, Won Kyung CHO, Dong-Gun KIM, Eun Hee PARK
  • Publication number: 20190334355
    Abstract: The present application relates to a battery charging method and charging system which can prevent degradation of a battery and enhance the lifetime characteristics thereof. In one aspect, the charging method includes charging a battery at a first C-rate higher than a reference C-rate, wherein the C-rate represents charge or discharge current/a rated capacity of the battery. The charging method also includes charging the battery at a second C-rate lower than the reference C-rate. The charging of the battery at the first C-rate includes at least one rest period for temporarily stopping the charging of the battery.
    Type: Application
    Filed: July 8, 2019
    Publication date: October 31, 2019
    Inventors: Dong Rak KIM, Jung Gun PARK, Jung Pil PARK
  • Publication number: 20190326627
    Abstract: Disclosed is a method of manufacturing a solid electrolyte for an all-solid battery. The method may include preparing a solvent admixture comprising a first polar organic solvent containing a cyano group and a second polar organic solvent containing a hydroxyl group, preparing an electrolyte admixture by dissolving Li2S, P2S5 and LiCl in the solvent admixture, and preparing a solid electrolyte by stirring the electrolyte admixture. The method may further include precipitating the solid electrolyte by evaporating the solvent admixture, and heat treating the precipitated solid electrolyte. In particular, the solvent admixture may include the second polar organic solvent in an amount of about 0.01 to 0.03 wt % based on the total weight of the first polar organic solvent.
    Type: Application
    Filed: December 5, 2018
    Publication date: October 24, 2019
    Inventors: Ju Yeong Seong, Hong Seok Min, Yong Jun Jang, Yong Sub Yoon, Pil Gun Oh, Dong Wook Shin, Sun Ho Choi, Jong Yeob Park
  • Patent number: 10360992
    Abstract: A test device includes a data driver and a controller. The controller is configured to generate a test code by dividing a test sequence in a unit of n-bits. The data driver is configured to receive the generated test code and output one of input voltages to a device under test as a test signal based on the generated test code. A storage device stores a test sequence.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: July 23, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Gun Kim, Je-Young Park, Byung-Soo Moon
  • Publication number: 20190198917
    Abstract: The present invention relates to a nitrogen-doped sulfide-based solid electrolyte for all-solid batteries. The a nitrogen-doped sulfide-based solid electrolyte for all-solid batteries includes a compound with an argyrodite-type crystal structure represented by the following Formula 1: LiaPSbNcXd??[Formula 1] wherein 6?a?7, 3<b<6, 0<c?1, 0<d?2, and each X is the same or different halogen atom selected from the group consisting of chlorine (Cl), bromine (Br), and iodine (I).
    Type: Application
    Filed: October 17, 2018
    Publication date: June 27, 2019
    Inventors: Ju Yeong Seong, Yong Jun Jang, Hong Seok Min, Sa Heum Kim, Yong Sub Yoon, Pil Gun Oh, Dong Wook Shin, Chan Hwi Park, Jin Oh Son
  • Publication number: 20190189804
    Abstract: A semiconductor device includes first and second fin patterns on a substrate and extending apart from each other, a field insulating film on the substrate and surrounding parts of the first and second fin patterns, a first gate structure on the first fin pattern and intersecting the first fin pattern, a second gate structure on the second fin pattern and intersecting the second fin pattern, and a separating structure protruding from a top surface of the field insulating film and separating the first and second gate structures, the field insulating film and the separating structure including a same insulating material.
    Type: Application
    Filed: July 25, 2018
    Publication date: June 20, 2019
    Inventors: Jung Gun YOU, Dong Hyun KIM, Byoung-Gi KIM, Yun Suk NAM, Yeong Min JEON, Sung Chul PARK, Dae Won HA
  • Publication number: 20170220162
    Abstract: A display device includes a display panel and a first sensor configured to sense a position of a touch of a user and a second sensor configured to sense a pressure of the touch. The first sensor and the second sensor may be provided inside or surrounding an area of the display panel. The second sensor includes a first conductor, a second conductor spaced apart from the first conductor, and configured to form capacitance with the first conductor, and one or more variable resistance elements connected with the first conductor.
    Type: Application
    Filed: November 15, 2016
    Publication date: August 3, 2017
    Inventors: Jun Young KO, Dong Gun PARK, Jin Oh KWAG, Young Sik Kim, Tae Joon Kim
  • Patent number: 9012982
    Abstract: A recessed transistor and a method of manufacturing the same are provided. The recessed transistor may include a substrate, an active pin, a gate pattern and source and drain regions. The substrate may include an isolation layer that establishes an active region and a field region of the substrate. The substrate may include a recessed structure having an upper recess formed in the active region and a lower recess in communication with the upper recess. An active pin may be formed in a region between side surfaces of the isolation layer and the lower recess and an interface between the active region and the field region. The gate pattern may include a gate insulation layer formed on an inner surface of the recessed structure and a gate electrode formed on the gate insulation layer in the recessed structure. The source/drain regions may be formed adjacent to the active region and the gate electrode.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: April 21, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Keun-Nam Kim, Makoto Yoshida, Chul Lee, Dong-Gun Park, Woun-Suck Yang
  • Patent number: 8815702
    Abstract: Semiconductor devices include a semiconductor substrate with a stack structure protruding from the semiconductor substrate and surrounded by an isolation structure. The stack structure includes an active layer pattern and a gap-filling insulation layer between the semiconductor substrate and the active layer pattern. A gate electrode extends from the isolation structure around the stack structure. The gate electrode is configured to provide a support structure for the active layer pattern. The gate electrode may be a gate electrode of a silicon on insulator (SOI) device formed on the semiconductor wafer and the semiconductor device may further include a bulk silicon device formed on the semiconductor substrate in a region of the semiconductor substrate not including the gap-filing insulation layer.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: August 26, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Woo Oh, Dong-Gun Park, Dong-Won Kim, Ming Li, Sung-Hwan Kim
  • Patent number: 8552488
    Abstract: Nonvolatile memory devices are provided including an integrated circuit substrate and a charge storage pattern on the integrated circuit substrate. The charge storage pattern has a sidewall and a tunnel insulating layer is provided between the charge storage pattern and the integrated circuit substrate. A gate pattern is provided on the charge storage pattern. A blocking insulating layer is provided between the charge storage pattern and the gate pattern. The sidewall of the charge storage pattern includes a first nitrogen doped layer. Related methods of fabricating nonvolatile memory devices are also provided herein.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: October 8, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Hyun Lee, Dong-Gun Park
  • Patent number: 8482045
    Abstract: Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F2 structure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: July 9, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-won Seo, Bong-soo Kim, Dong-gun Park, Kang-yoon Lee, Jae-man Yoon, Seong-goo Kim, Seung-bae Park