Patents by Inventor Dong-Gun Park

Dong-Gun Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240335678
    Abstract: The present invention relates to a conversion device for converting a treatment beam for treating a lesion of a subject, comprising: a collimator unit to which the treatment beam is incident and which has a plurality of slits; and a scattering unit that scatters the treatment beam that has passed through the collimator unit.
    Type: Application
    Filed: June 23, 2022
    Publication date: October 10, 2024
    Applicants: NATIONAL CANCER CENTER, RAPHARAD INC., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY, SAMSUNG LIFE PUBLIC WELFARE FOUNDATION
    Inventors: Young Kyung LIM, Myeong Soo KIM, Kyeong Yun PARK, Do Hyeon KIM, Sang Soo KIM, Hak Soo KIM, Jong Hwi JEONG, Se Byeong LEE, Dong Ho SHIN, Joo Young KIM, Tae Hyun KIM, Seong Ho MOON, Yang-Gun SUH, Hojin KIM, Kwanghyun JO
  • Patent number: 12102451
    Abstract: The present invention relates to an integrated circuit for processing biosignals, a biosignal processing apparatus, and a biosignal processing system, and the integrated circuit includes: a digital conversion unit for converting an analog biosignal input through a biosignal input terminal into digital biodata; and an AI block for processing a plurality of biodatas converted through the digital conversion unit according to an artificial intelligence processing flow, and outputting a result data according to processing of the plurality of biodatas.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: October 1, 2024
    Assignees: SKAIChips Co., Ltd., Research & Business Foundation SUNGSKYUNKWAN UNIVERSITY
    Inventors: Kang Yoon Lee, Jong Wan Jo, Young Gun Pu, Imran Ali, Dong Gyu Kim, Joon Hong Park, Dong Gyun Kim, Yun Gwan Kim, Jae Bin Kim, Dong Soo Park, Sung June Byun
  • Patent number: 10747345
    Abstract: A display device includes a display panel and a first sensor configured to sense a position of a touch of a user and a second sensor configured to sense a pressure of the touch. The first sensor and the second sensor may be provided inside or surrounding an area of the display panel. The second sensor includes a first conductor, a second conductor spaced apart from the first conductor, and configured to form capacitance with the first conductor, and one or more variable resistance elements connected with the first conductor.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: August 18, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jun Young Ko, Dong Gun Park, Jin Oh Kwag, Young Sik Kim, Tae Joon Kim
  • Publication number: 20170220162
    Abstract: A display device includes a display panel and a first sensor configured to sense a position of a touch of a user and a second sensor configured to sense a pressure of the touch. The first sensor and the second sensor may be provided inside or surrounding an area of the display panel. The second sensor includes a first conductor, a second conductor spaced apart from the first conductor, and configured to form capacitance with the first conductor, and one or more variable resistance elements connected with the first conductor.
    Type: Application
    Filed: November 15, 2016
    Publication date: August 3, 2017
    Inventors: Jun Young KO, Dong Gun PARK, Jin Oh KWAG, Young Sik Kim, Tae Joon Kim
  • Patent number: 9012982
    Abstract: A recessed transistor and a method of manufacturing the same are provided. The recessed transistor may include a substrate, an active pin, a gate pattern and source and drain regions. The substrate may include an isolation layer that establishes an active region and a field region of the substrate. The substrate may include a recessed structure having an upper recess formed in the active region and a lower recess in communication with the upper recess. An active pin may be formed in a region between side surfaces of the isolation layer and the lower recess and an interface between the active region and the field region. The gate pattern may include a gate insulation layer formed on an inner surface of the recessed structure and a gate electrode formed on the gate insulation layer in the recessed structure. The source/drain regions may be formed adjacent to the active region and the gate electrode.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: April 21, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Keun-Nam Kim, Makoto Yoshida, Chul Lee, Dong-Gun Park, Woun-Suck Yang
  • Patent number: 8815702
    Abstract: Semiconductor devices include a semiconductor substrate with a stack structure protruding from the semiconductor substrate and surrounded by an isolation structure. The stack structure includes an active layer pattern and a gap-filling insulation layer between the semiconductor substrate and the active layer pattern. A gate electrode extends from the isolation structure around the stack structure. The gate electrode is configured to provide a support structure for the active layer pattern. The gate electrode may be a gate electrode of a silicon on insulator (SOI) device formed on the semiconductor wafer and the semiconductor device may further include a bulk silicon device formed on the semiconductor substrate in a region of the semiconductor substrate not including the gap-filing insulation layer.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: August 26, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Woo Oh, Dong-Gun Park, Dong-Won Kim, Ming Li, Sung-Hwan Kim
  • Patent number: 8552488
    Abstract: Nonvolatile memory devices are provided including an integrated circuit substrate and a charge storage pattern on the integrated circuit substrate. The charge storage pattern has a sidewall and a tunnel insulating layer is provided between the charge storage pattern and the integrated circuit substrate. A gate pattern is provided on the charge storage pattern. A blocking insulating layer is provided between the charge storage pattern and the gate pattern. The sidewall of the charge storage pattern includes a first nitrogen doped layer. Related methods of fabricating nonvolatile memory devices are also provided herein.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: October 8, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Hyun Lee, Dong-Gun Park
  • Patent number: 8482045
    Abstract: Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F2 structure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: July 9, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-won Seo, Bong-soo Kim, Dong-gun Park, Kang-yoon Lee, Jae-man Yoon, Seong-goo Kim, Seung-bae Park
  • Patent number: 8466511
    Abstract: A fin field-effect transistor (FinFET) device includes a fin-shaped active region having first and second source/drain regions therein and a channel region therebetween vertically protruding from a semiconductor substrate. A gate electrode is formed on an upper surface and sidewalls of the channel region. First and second source/drain contacts are formed on respective upper surfaces and sidewalls of the first and second source/drain regions of the fin-shaped active region at opposite sides of the gate electrode. The channel region may be narrower than the first and second source/drain regions of the fin-shaped active region.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: June 18, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Woo Oh, Dong-Gun Park, Sung-Young Lee, Jeong-Dong Choe, Dong-Won Kim
  • Patent number: 8461653
    Abstract: A semiconductor device may include a substrate, an active semiconductor region of the substrate, and a gate electrode. The active semiconductor region may include a channel region between first and second junction regions. The channel region may include a first semiconductor material, the first and second junction regions may include a second semiconductor material, and the first and second semiconductor materials may be different. The gate electrode may be on the channel region with portions of the first and second junction regions being free of the gate electrode.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: June 11, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-woo Oh, Dong-gun Park, Dong-won Kim, Sung-dae Suk
  • Patent number: 8445959
    Abstract: A semiconductor device includes a substrate, a gate insulation layer, a gate structure, a gate spacer, and first and second impurity regions. The substrate has an active region defined by an isolation layer. The active region has a gate trench thereon. The gate insulation layer is formed on an inner wall of the gate trench. The gate structure is formed on the gate insulation layer to fill the gate trench. The gate structure has a width smaller than that of the gate trench, and has a recess at a first portion thereof. The gate spacer is formed on sidewalls of the gate structure. The first and second impurity regions are formed at upper portions of the active region adjacent to the gate structure. The first impurity region is closer to the recess than the second impurity region. Related methods are also provided.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: May 21, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo-Young Lee, Dong-Gun Park
  • Patent number: 8426901
    Abstract: Semiconductor devices include a semiconductor substrate with a stack structure protruding from the semiconductor substrate and surrounded by an isolation structure. The stack structure includes an active layer pattern and a gap-filling insulation layer between the semiconductor substrate and the active layer pattern. A gate electrode extends from the isolation structure around the stack structure. The gate electrode is configured to provide a support structure for the active layer pattern. The gate electrode may be a gate electrode of a silicon on insulator (SOI) device formed on the semiconductor wafer and the semiconductor device may further include a bulk silicon device formed on the semiconductor substrate in a region of the semiconductor substrate not including the gap-filing insulation layer.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: April 23, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-woo Oh, Dong-gun Park, Dong-won Kim, Ming Li, Sung-hwan Kim
  • Patent number: 8415210
    Abstract: A field effect transistor (FET) and a method for manufacturing the same, in which the FET may include an isolation film formed on a semiconductor substrate to define an active region, and a gate electrode formed on a given portion of the semiconductor substrate. A channel layer may be formed on a portion of the gate electrode, with source and drain regions formed on either side of the channel layer so that boundaries between the channel layer and the source and drain regions of the FET may be perpendicular to a surface of the semiconductor substrate.
    Type: Grant
    Filed: October 29, 2011
    Date of Patent: April 9, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Woo Oh, Dong-Gun Park, Dong-Won Kim, Dong-Uk Choi, Kyoung-Hwan Yeo
  • Patent number: 8344367
    Abstract: Molecular devices and methods of manufacturing the molecular device are provided. The molecular device may include a lower electrode on a substrate and a self-assembled monolayer on the lower electrode. After an upper electrode is formed on the self-assembled monolayer, the self-assembled monolayer may be removed to form a gap between the lower electrode and the upper electrode. A functional molecule having a functional group may be injected into the gap.
    Type: Grant
    Filed: January 3, 2011
    Date of Patent: January 1, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Won Kim, Dong-Gun Park, Sung-Young Lee, Yang-Kyu Choi, Lee-Eun Yu
  • Publication number: 20120305997
    Abstract: A semiconductor device includes a substrate, a gate insulation layer, a gate structure, a gate spacer, and first and second impurity regions. The substrate has an active region defined by an isolation layer. The active region has a gate trench thereon. The gate insulation layer is formed on an inner wall of the gate trench. The gate structure is formed on the gate insulation layer to fill the gate trench. The gate structure has a width smaller than that of the gate trench, and has a recess at a first portion thereof. The gate spacer is formed on sidewalls of the gate structure. The first and second impurity regions are formed at upper portions of the active region adjacent to the gate structure. The first impurity region is closer to the recess than the second impurity region. Related methods are also provided.
    Type: Application
    Filed: August 15, 2012
    Publication date: December 6, 2012
    Inventors: Joo-Young Lee, Dong-Gun Park
  • Publication number: 20120273898
    Abstract: Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device.
    Type: Application
    Filed: July 16, 2012
    Publication date: November 1, 2012
    Inventors: Hyeoung-won Seo, Bong-soo Kim, Dong-gun Park, Kang-yoon Lee, Jae-man Yoon, Seong-goo Kim, Seung-bae Park
  • Patent number: 8298899
    Abstract: Exposed are a semiconductor device and method of fabricating the same. The device includes an insulation film that is disposed between an active pattern and a substrate, which provides various improvements. This structure enhances the efficiency of high integration and offers an advanced structure for semiconductor devices.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: October 30, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Woo Oh, Sung-Hwan Kim, Dong-Gun Park
  • Patent number: 8293604
    Abstract: Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: October 23, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-man Yoon, Dong-gun Park, Choong-Ho Lee, Seong-Goo Kim, Won-sok Lee, Seung-bae Park
  • Patent number: 8283714
    Abstract: Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F2 structure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: October 9, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-won Seo, Bong-soo Kim, Dong-gun Park, Kang-yoon Lee, Jae-man Yoon, Seong-goo Kim, Seung-bae Park
  • Patent number: 8268690
    Abstract: A semiconductor device includes a substrate, a gate insulation layer, a gate structure, a gate spacer, and first and second impurity regions. The substrate has an active region defined by an isolation layer. The active region has a gate trench thereon. The gate insulation layer is formed on an inner wall of the gate trench. The gate structure is formed on the gate insulation layer to fill the gate trench. The gate structure has a width smaller than that of the gate trench, and has a recess at a first portion thereof. The gate spacer is formed on sidewalls of the gate structure. The first and second impurity regions are formed at upper portions of the active region adjacent to the gate structure. The first impurity region is closer to the recess than the second impurity region. Related methods are also provided.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: September 18, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo-Young Lee, Dong-Gun Park