Abstract: Provided are methods for fabricating semiconductor devices incorporating a fin-FET structure that provides body-bias control, exhibits some characteristic advantages associated with SOI structures, provides increased operating current and/or reduced contact resistance. The methods for fabricating semiconductor devices include forming insulating spacers on the sidewalls of a protruding portion of a first insulation film; forming a second trench by removing exposed regions of the semiconductor substrate using the insulating spacers as an etch mask, and thus forming fins in contact with and supported by the first insulation film. After forming the fins, a third insulation film is formed to fill the second trench and support the fins. A portion of the first insulation film is then removed to open a space between the fins in which additional structures including gate dielectrics, gate electrodes and additional contact, insulating and storage node structures may be formed.

Abstract: A semiconductor device may include a fin structure having source/drain regions and channel fins connected between source/drain patterns. A gate insulation layer may be provided on the channel fins. A gate electrode may include lower gate patterns and an upper gate pattern. The lower gate patterns may extend in a vertical direction and contact the gate insulation layer. The upper gate pattern may extend in a second horizontal direction substantially perpendicular to the first horizontal direction. The upper gate pattern may be connected to upper portions of the lower gate patterns.

Abstract: An integrated circuit device includes a substrate. An epitaxial pattern is on the substrate and has a pair of impurity diffusion regions formed therein and a pair of void regions formed therein that are disposed between the pair of impurity diffusion regions and the substrate. Respective ones of the pair of impurity diffusion regions at least partially overlap respective ones of the pair of void regions. A gate electrode is on the epitaxial pattern between respective ones of the pair of impurity diffusion regions.

Abstract: Molecular devices and methods of manufacturing the molecular device are provided. The molecular device may include a lower electrode on a substrate and a self-assembled monolayer on the lower electrode. After an upper electrode is formed on the self-assembled monolayer, the self-assembled monolayer may be removed to form a gap between the lower electrode and the upper electrode. A functional molecule having a functional group may be injected into the gap.

Abstract: A recessed transistor and a method of manufacturing the same are provided. The recessed transistor may include a substrate, an active pin, a gate pattern and source and drain regions. The substrate may include an isolation layer that establishes an active region and a field region of the substrate. The substrate may include a recessed structure having an upper recess formed in the active region and a lower recess in communication with the upper recess. An active pin may be formed in a region between side surfaces of the isolation layer and the lower recess and an interface between the active region and the field region. The gate pattern may include a gate insulation layer formed on an inner surface of the recessed structure and a gate electrode formed on the gate insulation layer in the recessed structure. The source/drain regions may be formed adjacent to the active region and the gate electrode.

Abstract: A memory device may include a substrate, a bit line, at least a first lower word line, at least a first trap site, a pad electrode, at least a first cantilever electrode, and/or at least a first upper word line. The bit line may be formed on the substrate in a first direction. The first lower word line and the first trap site may be insulated from the bit line and formed in a second direction crossing the bit line. The pad electrode may be insulated at sidewalls of the first lower word line and the first trap site and connected to the bit line. The first cantilever electrode may be formed in the first direction, connected to the pad electrode, floated on the first trap site with at least a first lower vacant space, and/or configured to be bent in a third direction. The first upper word line may be formed on the first cantilever electrode in the second direction with at least a first upper vacant space.

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a lower layer and an upper layer overlying the lower layer. The upper layer is arranged and structured to form first and second active regions that are spaced apart from each other and protrude from an upper surface of the lower layer. A third active region of a bridge shape is distanced vertically from the upper surface of the lower layer and connects the first and second active regions. The device further includes a gate electrode, which is formed with a gate insulation layer surrounding the third active region, so that the third active region functions as a channel.

Abstract: According to a nonvolatile memory device having a multi gate structure and a method for forming the same of the present invention, a gate electrode is formed using a damascene process. Therefore, a charge storage layer, a tunneling insulating layer, a blocking insulating layer and a gate electrode layer are not attacked from etching in a process for forming the gate electrode, thereby forming a nonvolatile memory device having good reliability.

Abstract: An elongate stacked semiconductor structure is formed on a substrate. The stacked semiconductor structure includes a second semiconductor material region disposed on a first semiconductor material region. The first semiconductor material region is selectively doped to produce spaced-apart impurity-doped first semiconductor material regions and a lower dopant concentration first semiconductor material region therebetween. Etching exposes a portion of the second semiconductor material region between the impurity-doped first semiconductor material regions. The etching removes at least a portion of the lower dopant concentration first semiconductor material region to form a hollow between the substrate and the portion of the second semiconductor material region between the impurity-doped first semiconductor material regions. An insulation layer that surrounds the exposed portion of the second semiconductor material region between the impurity-doped first semiconductor material regions is formed.

Abstract: A self-aligned contact structure and a method of forming the same include selected neighboring gate electrodes with adjacent sidewalls that are configured to angle toward each other. The angled surfaces of the gate electrodes can be protected using a liner layer that can extend the length of the contact window to define the sidewalls of the contact window.

Abstract: Embodiments of the invention include a partially insulated field effect transistor and a method of fabricating the same. According to some embodiments, a semiconductor substrate is formed by sequentially stacking a bottom semiconductor layer, a sacrificial layer, and a top semiconductor layer. The sacrificial layer may be removed to form a buried gap region between the bottom semiconductor layer and the top semiconductor layer. Then, a transistor may be formed on the semiconductor substrate. The sacrificial layer may be a crystalline semiconductor formed by an epitaxial growth technology.

Abstract: There are provided a multi-bit electromechanical memory device capable of enhancing or maximizing a degree of integration of the memory device and a method of manufacturing the multi-bit electromechanical memory device which includes a substrate, a bit line on the substrate, and extending in a first direction; a word line on the bit line, insulated from the bit line, and extending in a second direction transverse to the first direction, and a cantilever electrode including a shape memory alloy. The cantilever electrode has a first portion electrically connected to the bit line and a second portion extending in the first direction, and spaced apart from the word line by an air gap, wherein the cantilever electrode, in a first state, is in electrical contact with the word line, and, in a second state, is spaced apart from the word line.

Abstract: In a semiconductor memory device having a vertical channel transistor a body of which is connected to a substrate and a method of fabricating the same, the semiconductor memory device includes a semiconductor substrate including a plurality of pillars arranged spaced apart from one another, and each of the pillars includes a body portion and a pair of pillar portions extending from the body portion and spaced apart from each other. A gate electrode is formed to surround each of the pillar portions. A bitline is disposed on the body portion to penetrate a region between a pair of the pillar portions of each of the first pillars arranged to extend in a first direction. A wordline is disposed over the bitline, arranged to extend in a second direction intersecting the first direction, and configured to contact the side surface of the gate electrode. A first doped region is formed in the upper surface of each of the pillar portions of the pillar.

Abstract: An integrated circuit device containing complementary metal oxide semiconductor transistors includes a semiconductor substrate and an NMOS transistor having a first fin-shaped active region that extends in the semiconductor substrate. The first fin-shaped active region has a first channel region therein with a first height. A PMOS transistor is also provided. The PMOS transistor has a second fin-shaped active region that extends in the semiconductor substrate. This second fin-shaped active region has a second channel region therein with a second height unequal to the first height.

Abstract: Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate electrode surrounds the channels and extends through the at least one tunnel. A pair of source/drain regions also is provided. Integrated circuit field effect transistors are manufactured, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The interchannel layers are selectively removed to form tunnels. A gate electrode is formed in the tunnels and surrounding the channels.

Abstract: Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.

Abstract: In a flash memory device, which can maintain an enhanced electric field between a control gate and a storage node (floating gate) and has a reduced cell size, and a method of manufacturing the flash memory device, the flash memory device includes a semiconductor substrate having a pair of drain regions and a source region formed between the pair of drain regions, a pair of spacer-shaped control gates each formed on the semiconductor substrate between the source region and each of the drain regions, and a storage node formed in a region between the control gate and the semiconductor substrate. A bottom surface of each of the control gates includes a first region that overlaps with the semiconductor substrate and a second region that overlaps with the storage node. The pair of spacer-shaped control gates are substantially symmetrical with each other about the source region.

Abstract: In a semiconductor device and a method of fabricating the same, a vertical channel transistor has a cell occupation area of 4F2.

Abstract: A non-volatile memory device, and method of forming the same, increases or maximizes the performance of an ultramicro-structured device.

Abstract: In a method of manufacturing a semiconductor device, a preliminary active pattern including gate layers and channel layers is formed on a substrate. The gate layers and the channel layers are alternatively stacked. A hard mask is formed on the preliminary active pattern. The preliminary active pattern is partially etched using the hard mask as an etching mask to expose a surface of the substrate. The etched preliminary active pattern is trimmed to form an active channel pattern having a width less than a lower width of the hard mask. Source/drain layers are formed on exposed side faces of the active channel pattern and the surface. The gate layers are selectively etched to form tunnels. A gate encloses the active channel pattern and filling the tunnels. Related intermediate structures are also disclosed.