Abstract: An apparatus and method for watermarking that uses elemental images of an integrated image having three-dimensional information as a watermark are disclosed. The watermarking apparatus in accordance with an embodiment of the present invention includes i) a computational pickup unit, which picks up an elemental image watermark computationally by placing an object three-dimensionally, ii) an embedding process unit, which embeds into a two-dimensional image the elemental image watermark obtained by the computational pickup unit, iii) an extraction process unit, which extracts the elemental image watermark by receiving through a transmission channel the watermarked two-dimensional image embedded by the embedding process unit, and iv) a computational reconstruction unit, which computationally reconstructs the elemental image watermark extracted by the extraction process unit to a distance-based image.

Abstract: A semiconductor memory device includes a memory cell array block including a plurality of memory cells each connected to one of a plurality of bit lines and one of a plurality of word lines, a sense amplifier connected to a half of the plurality of bit lines, the sense amplifier for sensing and amplifying a voltage between each of the half of the bit lines and a corresponding complementary bit line; and a dummy block connected to the half of the plurality of bit lines of the memory cell array block, the dummy block for controlling a load on the memory cell array block to be different from a load on the dummy block according to a dummy load signal.

Abstract: A semiconductor memory device has a single input terminal to select a buffer and includes input-output terminals, input-output buffers, a memory core, and a buffer selecting unit. The input-output terminals include address input terminals, data input-output terminals and an input terminal to select a buffer. The input-output buffers are coupled to the data input-output terminals respectively. The memory core is coupled to the input-output buffers through input-output lines. The buffer selecting unit generates a parallel buffer select signal based on an expected signal having a pulse stream, wherein the expected signal is provided via the input terminal to select a buffer in a test mode, and applies the parallel buffer select signal to the plurality of input-output buffers to select a corresponding input-output buffer. Hence, the semiconductor memory device may increase efficiency of a pin in a test device.

Abstract: A semiconductor device includes a bit line connected to a plurality of memory cells in a memory block and a sense amplifier having a first node connected to the bit line and a second node, which is not connected to any bit line. The second node has a capacitive load less than that of the bit line. The sense amplifier amplifies a first data using a voltage difference between the first node and the second node caused by a charge sharing operation, and a second data using a capacitive mismatch between the first node and the second node.

Abstract: A semiconductor memory device includes a first memory block, a second memory block, and a signal controller. The first memory block is configured to generate a first blocking signal, a second blocking signal, and a first enable signal in response to a row address, and to block and enable wordlines of the memory block in response to the first blocking signal and the first enable signal, respectively. The second memory block is configured to generate a third blocking signal, a fourth blocking signal, and a second enable signal in response to the row address, and to block and enable wordlines of the second memory block in response to the third blocking signal and the second enable signal, respectively. The signal controller is connected between the first memory block and the second memory block and is configured to enable the third blocking signal when the second blocking signal is enabled, and to enable the first blocking signal when the fourth blocking signal is enabled.

Abstract: A driver circuit for an integrated circuit device includes a transistor that has a gate terminal, a source terminal, and a bulk substrate terminal. The source terminal is connected to the bulk substrate terminal. A pull-up circuit is connected between a power supply node and the source terminal. The pull up circuit is configured to increase a voltage at the source terminal and the bulk substrate terminal of the transistor responsive to a control signal.

Abstract: A two dimensional to three dimensional (2D-3D) convertible display device is disclosed. In one embodiment, the display device includes i) a first display unit configured to selectively output one of a composite image and backlight, wherein the composite image comprises a background image and a mask image, for an object, wherein the background image comprises element images for a background excluding the object and wherein the mask image is a white image which has the same shape as that of the object, ii) a lens unit configured to convert the composite image into a stereoscopic image or pass through the backlight and iii) a second display unit configured to output i) a two-dimensional (2D) image of the object by the use of the backlight at a 2D mode and ii) the combination of the 2D image and the composite image at a three dimensional (3D) mode.

Abstract: A semiconductor memory device includes a row decoder, a control circuit, and a memory cell array having an open bit-line structure. The memory cell array includes a plurality of word lines coupled to the row decoder, a plurality of bit lines, a plurality of memory cells, a plurality of sense amplifier blocks, and a plurality of burn-in voltage supply lines coupled to the plurality of sense amplifier blocks in a predetermined order, respectively. The control circuit controls the row decoder and the memory cell array for performing a burn-in test. During the burn-in test, the burn-in voltage supply lines are provided with at least two different burn-in voltages. The burn-in voltage supply lines respectively coupled to the sense amplifier blocks that are adjacent to each other are provided with different burn-in voltages during the burn-in test.

Abstract: A three-dimensional image display method is disclosed. The three-dimensional image display method in accordance with an embodiment of the present invention includes: displaying an object image; displaying a background image by using a three-dimensional image display method; and disposing the object image at a close distance and the background image at a far distance such that the object image and the background image overlap inside a same viewing angle. By using images having a different sense of depth, a high-resolution image can be displayed while providing a sense of reality.

Abstract: A three-dimensional image display apparatus using an intermediate elemental image is disclosed. In one embodiment, the three-dimensional image display apparatus includes: i) an image input unit, generating a plurality of elemental images extracted from a three-dimensional object, the elemental images have different perspectives, ii) an image processing unit, generating an intermediate elemental image, using parallax information between the elemental images inputted from the image input unit and iii) an image reproduction unit, reproducing a three-dimensional image corresponding to the three-dimensional object, using the elemental image and the intermediate elemental image. With the three-dimensional image display apparatus, and the method thereof, using an intermediate elemental image in accordance with at least one embodiment of the present invention, a high-resolution three-dimensional image can be outputted.

Abstract: A semiconductor memory device may include a switching unit to selectively connect a bitline pair and a pair of input/output lines in response to a column selection line signal; a column selection line voltage generator to generate a column selection line voltage; and a column selection line driver to provide the column selection line signal based at least in at the column selection line voltage level.

Abstract: A driver circuit for an integrated circuit device includes a transistor that has a gate terminal, a source terminal, and a bulk substrate terminal. The source terminal is connected to the bulk substrate terminal. A pull-up circuit is connected between a power supply node and the source terminal. The pull up circuit is configured to increase a voltage at the source terminal and the bulk substrate terminal of the transistor responsive to a control signal.

Abstract: An apparatus and method for watermarking that uses elemental images of an integrated image having three-dimensional information as a watermark are disclosed. The watermarking apparatus in accordance with an embodiment of the present invention includes i) a computational pickup unit, which picks up an elemental image watermark computationally by placing an object three-dimensionally, ii) an embedding process unit, which embeds into a two-dimensional image the elemental image watermark obtained by the computational pickup unit, iii) an extraction process unit, which extracts the elemental image watermark by receiving through a transmission channel the watermarked two-dimensional image embedded by the embedding process unit, and iv) a computational reconstruction unit, which computationally reconstructs the elemental image watermark extracted by the extraction process unit to a distance-based image.

Abstract: A semiconductor memory device includes a memory cell array, and first and second boosting voltage generating portions. The first boosting voltage generating portion generates a first driving signal when the semiconductor device operates in an active mode and supplies a boosting voltage that is higher than a power supply voltage to an output terminal in response to the first driving signal. The second boosting voltage generating portion includes a first boosting voltage generator generating a second driving signal when a level of the boosting voltage of the output terminal is below a target level in the active mode and pumping the boosting voltage in response to the second driving signal and a second boosting voltage generator pumping the boosting voltage in response to the first driving signal when first memory cell array blocks are selected and pumping the boosting voltage in response to the second driving signal when second memory cell array blocks are selected.

Abstract: A data access circuit of a semiconductor memory device in which data is read and written via all multiple ports in the semiconductor memory device having a multi-port structure. The data access circuit device having a multi-port structure comprises a write controller, a plurality of ports to receive serial data to be written, a plurality of read/write data control units, a plurality of write buffer units, a read controller, an input/output sense amplifier, and a plurality of read buffer units. Test time for the semiconductor memory device can be shortened by doubling the number of ports even in low frequency equipment, thus improving the throughput, by allowing data to be simultaneously and divisionally accessed via all ports, instead of accessing the data via a specified port at a time.

Abstract: A semiconductor memory device includes a row decoder, a control circuit, and a memory cell array having an open bit-line structure. The memory cell array includes a plurality of word lines coupled to the row decoder, a plurality of bit lines, a plurality of memory cells, a plurality of sense amplifier blocks, and a plurality of burn-in voltage supply lines coupled to the plurality of sense amplifier blocks in a predetermined order, respectively. The control circuit controls the row decoder and the memory cell array for performing a burn-in test. During the burn-in test, the burn-in voltage supply lines are provided with at least two different burn-in voltages. The burn-in voltage supply lines respectively coupled to the sense amplifier blocks that are adjacent to each other are provided with different burn-in voltages during the burn-in test.

Abstract: A semiconductor memory device has a single input terminal to select a buffer and includes input-output terminals, input-output buffers, a memory core, and a buffer selecting unit. The input-output terminals include address input terminals, data input-output terminals and an input terminal to select a buffer. The input-output buffers are coupled to the data input-output terminals respectively. The memory core is coupled to the input-output buffers through input-output lines. The buffer selecting unit generates a parallel buffer select signal based on an expected signal having a pulse stream, wherein the expected signal is provided via the input terminal to select a buffer in a test mode, and applies the parallel buffer select signal to the plurality of input-output buffers to select a corresponding input-output buffer. Hence, the semiconductor memory device may increase efficiency of a pin in a test device.

Abstract: A semiconductor memory device has a single input terminal to select a buffer and includes input-output terminals, input-output buffers, a memory core, and a buffer selecting unit. The input-output terminals include address input terminals, data input-output terminals and an input terminal to select a buffer. The input-output buffers are coupled to the data input-output terminals respectively. The memory core is coupled to the input-output buffers through input-output lines. The buffer selecting unit generates a parallel buffer select signal based on an expected signal having a pulse stream, wherein the expected signal is provided via the input terminal to select a buffer in a test mode, and applies the parallel buffer select signal to the plurality of input-output buffers to select a corresponding input-output buffer. Hence, The semiconductor memory device may increase efficiency of a pin in a test device.

Abstract: A semiconductor memory device may include a switching unit to selectively connect a bitline pair and a pair of input/output lines in response to a column selection line signal; a column selection line voltage generator to generate a column selection line voltage; and a column selection line driver to provide the column selection line signal based at least in at the column selection line voltage level.

Abstract: A semiconductor memory device includes: a memory cell array including a plurality of memory cell array blocks in turn including first and second memory cell array blocks, the number of word lines activated when the first memory cell array blocks are selected being greater than the number of word lines activated when the second memory cell array blocks are selected; a first boosting voltage generating portion generating a first driving signal when the semiconductor device operates in an active mode and supplying a boosting voltage that is higher than a power supply voltage to an output terminal in response to the first driving signal; and a second boosting voltage generating portion including first and second boosting voltage generators, the first boosting voltage generator generating a second driving signal when a level of the boosting voltage of the output terminal is below a target level in the active mode and pumping the boosting voltage in response to the second driving signal, the second boosting voltage