Abstract: A method of forming floating gates having a high capacitance is provided. In this method, a tunnel oxide layer, a polycrystalline silicon layer, an interlayer oxide layer, and a silicon nitride layer are sequentially formed on a semiconductor substrate having isolation regions in the non-active region. A plurality of silicon nitride layer patterns which are separated from each other by predetermined distances, is formed by etching the silicon nitride layer. The surface of the polycrystalline silicon layer is exposed by etching the interlayer oxide layer using the silicon nitride layer patterns as an etch mask, thereby forming a plurality of interlayer oxide layer patterns. Sidewall spacers are formed on the sidewalls of the silicon nitride layer patterns and the interlayer oxide layer patterns. A mask is formed on the exposed surface of the polycrystalline silicon layer. The silicon nitride layer patterns and the sidewall spacers are removed.

Abstract: A trench isolation method is provided that prevents the formation of a dent between a trench isolation region and an active region and prevents the generation of water spots during a cleaning process. In the trench isolation method, an undercut is formed in a stress-relief oxide pad pattern formed below a nitride layer pattern that defines an active region as a mask pattern. A nitride liner, which is a stress-buffer layer, is then formed around the undercut such that is conforms to the shape of the undercut. Thus, even though the stress-buffer layer is partially etched during the removal of the nitride the hard mask pattern, the stress-buffer layer is not etched to a position below the upper surface of the substrate. Also, an anti-reflection layer, which is the main source of water spots, is simultaneously removed in the formation of the undercut.

Abstract: An isolation method in the fabrication process of a semiconductor device is provided. The method forms an oxide layer as a buffer layer for reducing stress through chemical vapor deposition (CVD). By the method, a first pad oxide layer and a silicon nitride layer are formed on a semiconductor substrate, and then an silicon nitride layer pattern is formed by patterning, and undercuts are formed in the first pad oxide layer pattern. Subsequently, a second pad oxide layer is formed on the entire surface of the semiconductor substrate through CVD, and then spacers are formed on the sidewalls of both the patterned first pad oxide layer and silicon nitride layer and a field oxide layer is formed through thermal oxidation. Alternatively, a silicon layer is deposited without the spacers to form the field oxide layer. The second pad oxide layer is a buffer layer for buffering stress during formation of the field oxide layer.

Abstract: An isolation method for a highly-integrated semiconductor device includes growing an epitaxial layer on the entire surface of a semiconductor substrate including over a trench on which an oxide layer is formed, thereby leaving the inside of the trench empty. A portion of the epitaxial layer which is located over the trench is then oxidized to form an isolation region.

Abstract: Methods of forming field oxide isolation regions in a semiconductor substrate include the steps of exposing residual polysilicon defects contained within preliminary field oxide isolation regions and then performing a cleaning step to etch and reduce the size of the exposed defects (or eliminate the defects altogether). The preliminary field oxide isolation regions are then oxidized to preferably convert any remaining polysilicon defects into silicon dioxide and then a final oxide etching step is performed to define the shapes of the final field oxide isolation regions. Preferably, a pad oxide layer is formed on a face of a semiconductor substrate and then a masking layer is formed on the pad oxide layer, opposite the face of the substrate. The masking layer is then patterned to define an opening therein which exposes an upper surface of the pad oxide layer.

Abstract: Isolation regions are fabricated on a substrate by forming a pattern region on the substrate, exposing spaced apart first and second areas of the substrate. The second area is then covered, preferably using sidewall spacers formed adjacent sidewall portions of the pattern region, while a portion of the first area is left exposed. A first insulation region is then formed on the exposed portion of the first area. The second area is then exposed and a trench isolation region is formed at the second area. Preferably, the pattern region is formed by forming a masking layer on the substrate and patterning the masking layer using a single photolithographic mask. The first insulation layer preferably is formed by thermally oxidizing the exposed portion of the first area. Preferably, the first area is wider than the second area.

Abstract: In a device isolation method for a semiconductor device, after a pad oxide layer and a nitride layer are formed on a semiconductor substrate, the nitride layer located above the device isolation region is removed. An undercut is formed under the nitride by partially etching the pad oxide layer. After a first oxide layer is formed on the exposed substrate and a polysilicon spacer is formed on the sidewalls of the nitride layer, a void is formed in the oxide layer under the nitride layer which is formed on the active region by oxidizing the resultant structure in which the polysilicon spacer is formed at a temperature above 950.degree. C. Thus, good cell definition and stable device isolation can be realized, while solving the typical problem of conventional LOCOS methods by forming the void intentionally in the pad oxide layer thickened by bird's beak punch through.