Patents by Inventor Dong-Ho Han
Dong-Ho Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210335712Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate; a bridge, embedded in the package substrate, wherein the bridge includes an integral passive component, and wherein a surface of the bridge include first contacts in a first interconnect area and second contacts in a second interconnect area; a first die coupled to the passive component via the first contacts in the first interconnect area; and a second die coupled to the second contacts in the second interconnect area.Type: ApplicationFiled: July 9, 2021Publication date: October 28, 2021Applicant: Intel CorporationInventors: Amit Kumar Jain, Sameer Shekhar, Chin Lee Kuan, Kevin Joseph Doran, Dong-Ho Han
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Publication number: 20210327782Abstract: Methods and apparatus are disclosed to provide electrical shielding for integrated circuit packages using a thermal interface material. An integrated circuit package includes a substrate including a ground plane layer and a solder mask; a semiconductor die attached to the substrate, the solder mask layer separating the semiconductor die from the ground plane layer; and a thermal interface material surrounding at least a portion of the semiconductor die, the thermal interface material electrically coupled to the ground plane layer.Type: ApplicationFiled: June 25, 2021Publication date: October 21, 2021Inventors: Dong-Ho Han, Jaejin Lee, Jerrod Peterson, Kyle Arrington
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Patent number: 11133256Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate; a bridge, embedded in the package substrate, wherein the bridge includes an integral passive component, and wherein a surface of the bridge include first contacts in a first interconnect area and second contacts in a second interconnect area; a first die coupled to the passive component via the first contacts in the first interconnect area; and a second die coupled to the second contacts in the second interconnect area.Type: GrantFiled: June 20, 2019Date of Patent: September 28, 2021Assignee: Intel CorporationInventors: Amit Kumar Jain, Sameer Shekhar, Chin Lee Kuan, Kevin Joseph Doran, Dong-Ho Han
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Patent number: 11081450Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a substrate, a radiation source on the substrate, a ground on the substrate, where the ground is located around the radiation source, and a heat spreader over the radiation source, where the heat spreader includes one or more ground coupling mechanisms that are in contact with the ground on the substrate. The one or more ground coupling mechanisms in contact with the ground on the substrate create a radiation shield that at least partially keeps radiation from the radiation source from extending past the substrate.Type: GrantFiled: September 27, 2019Date of Patent: August 3, 2021Assignee: Intel CorporationInventors: Dong-Ho Han, Jaejin Lee, Je-Young Chang, Jerrod Peterson, Mark Carbone
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Publication number: 20210193598Abstract: A semiconductor package and a packaged electronic device are described. The semiconductor package has a foundation layer and a planar filtering circuit. The circuit is formed in the foundation layer to provide EMI/RFI mitigation. The circuit has one or more conductive traces that are patterned to form an equivalent circuit of inductors and capacitors. The one or more conductive traces include planar metal shapes, such as meanders, loops, inter-digital fingers, and patterned shapes, to reduce the z-height of the package. The packaged electronic device has a semiconductor die, a foundation layer, a motherboard, a package, and the circuit. The circuit removes undesirable interferences generated from the semiconductor die. The circuit has a z-height that is less than a z-height of solder balls used to attach the foundation layer to the motherboard. A method of forming a planar filtering circuit in a foundation layer is also described.Type: ApplicationFiled: March 5, 2021Publication date: June 24, 2021Inventors: Hao-Han HSU, Dong-Ho HAN, Steven C. WACHTMAN, Ryan K. KUHLMANN
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Patent number: 10991665Abstract: A semiconductor package and a packaged electronic device are described. The semiconductor package has a foundation layer and a planar filtering circuit. The circuit is formed in the foundation layer to provide EMI/RFI mitigation. The circuit has one or more conductive traces that are patterned to form an equivalent circuit of inductors and capacitors. The one or more conductive traces include planar metal shapes, such as meanders, loops, inter-digital fingers, and patterned shapes, to reduce the z-height of the package. The packaged electronic device has a semiconductor die, a foundation layer, a motherboard, a package, and the circuit. The circuit removes undesirable interferences generated from the semiconductor die. The circuit has a z-height that is less than a z-height of solder balls used to attach the foundation layer to the motherboard. A method of forming a planar filtering circuit in a foundation layer is also described.Type: GrantFiled: September 29, 2016Date of Patent: April 27, 2021Assignee: Intel CorporationInventors: Hao-Han Hsu, Dong-Ho Han, Steven C. Wachtman, Ryan K. Kuhlmann
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Publication number: 20210120665Abstract: Electromagnetic interference (EMI) shields having attenuation interfaces are disclosed. A disclosed example EMI shield includes side walls defining sides of the EMI shield, and an attenuation interface to be placed into contact with a circuit board. The attenuation interface includes an inner perimeter having an EMI absorber and an outer perimeter having a metal backing to at least partially surround the EMI absorber.Type: ApplicationFiled: December 23, 2020Publication date: April 22, 2021Inventors: Jaejin Lee, Isaac Simpson, Dong-Ho Han, Jose Salazar Delgado, Arturo Navarro Alvarez
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Patent number: 10950555Abstract: Semiconductor packages and a method of forming a semiconductor package are described. The semiconductor package has a foundation layer, a conductive layer formed in the foundation layer, and a magnetic layer formed between the conductive and the foundation layer. The conductive layer and the magnetic layer are coupled to form a low-profile inductor shield. The semiconductor package also has a dielectric layer formed between the magnetic and foundation layer. The foundation layer is mounted between a motherboard and a semiconductor die, where the foundation layer is attached to the motherboard with solder balls. Accordingly, the low-profile inductor shield may include a z-height that is less than a z-height of the solder balls. The low-profile inductor shield may have solder pads that are coupled to the conductive layer. The foundation layer may include at least one of voltage regulator and inductor, where the inductor is located above the low-profile inductor shield.Type: GrantFiled: March 30, 2017Date of Patent: March 16, 2021Assignee: Intel CorporationInventors: Kaladhar Radhakrishnan, Jaejin Lee, Hao-Han Hsu, Chung-Hao J. Chen, Dong-Ho Han
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Publication number: 20210057142Abstract: A coil component includes a support substrate, a coil portion including a first conductive layer being in contact with one surface of the support substrate, and a second conductive layer disposed on the first conductive layer to be spaced apart from the one surface of the support substrate, and a body including the support substrate and the coil portion embedded in the body. One side of the first conductive layer is closer to a center of the second conductive layer in a width direction of the coil portion than one side of the second conductive layer.Type: ApplicationFiled: June 5, 2020Publication date: February 25, 2021Inventors: Young Min Hur, Dong Ho Han, Boum Seock Kim
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Patent number: 10850960Abstract: The present invention is related to a cooling device for a forklift brake system, which is capable of maintaining a predetermined level of heat-radiation performance by reducing heat when heat is generated in a service brake that is provided at a forklift driving shaft. A cooling device for a forklift brake system according to an exemplary embodiment of the present invention allows cooling oil to bypass a cooler when a pressure of the cooling oil is abnormally increased or there is a concern that a pressure of the cooling oil is increased, thereby preventing the cooler from being damaged.Type: GrantFiled: December 8, 2015Date of Patent: December 1, 2020Inventor: Dong Ho Han
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Publication number: 20200165112Abstract: The present invention is related to a cooling device for a forklift brake system, which is capable of maintaining a predetermined level of heat-radiation performance by reducing heat when heat is generated in a service brake that is provided at a forklift driving shaft. A cooling device for a forklift brake system according to an exemplary embodiment of the present invention allows cooling oil to bypass a cooler when a pressure of the cooling oil is abnormally increased or there is a concern that a pressure of the cooling oil is increased, thereby preventing the cooler from being damaged.Type: ApplicationFiled: December 8, 2015Publication date: May 28, 2020Applicant: DOOSAN CORPORATIONInventor: Dong Ho HAN
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Patent number: 10645797Abstract: Embodiments herein disclose techniques for electronic apparatuses including a printed circuit board (PCB) and an electromagnetic interference (EMI) shield for the PCB. An electronic apparatus may include a PCB with a plurality of layers including a ground layer. The PCB may include a cutout through the plurality of layers of the PCB. An EMI shield may be mounted to a bottom side of the PCB along an edge of the cutout, where the EMI shield may be coupled to the ground layer through an ohmic contact. The EMI shield may be flat. Other embodiments may also be described and claimed.Type: GrantFiled: July 26, 2017Date of Patent: May 5, 2020Assignee: Intel CorporationInventors: Dong-Ho Han, Timothy Swettlen
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Publication number: 20200066658Abstract: A semiconductor package and a packaged electronic device are described. The semiconductor package has a foundation layer and a planar filtering circuit. The circuit is formed in the foundation layer to provide EMI/RFI mitigation. The circuit has one or more conductive traces that are patterned to form an equivalent circuit of inductors and capacitors. The one or more conductive traces include planar metal shapes, such as meanders, loops, inter-digital fingers, and patterned shapes, to reduce the z-height of the package. The packaged electronic device has a semiconductor die, a foundation layer, a motherboard, a package, and the circuit. The circuit removes undesirable interferences generated from the semiconductor die. The circuit has a z-height that is less than a z-height of solder balls used to attach the foundation layer to the motherboard. A method of forming a planar filtering circuit in a foundation layer is also described.Type: ApplicationFiled: September 29, 2016Publication date: February 27, 2020Inventors: Hao-Han HSU, Dong-Ho HAN, Steven C. WACHTMAN, Ryan K. KUHLMANN
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Publication number: 20200027844Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a substrate, a radiation source on the substrate, a ground on the substrate, where the ground is located around the radiation source, and a heat spreader over the radiation source, where the heat spreader includes one or more ground coupling mechanisms that are in contact with the ground on the substrate. The one or more ground coupling mechanisms in contact with the ground on the substrate create a radiation shield that at least partially keeps radiation from the radiation source from extending past the substrate.Type: ApplicationFiled: September 27, 2019Publication date: January 23, 2020Applicant: Intel CorporationInventors: Dong-Ho Han, Jaejin Lee, Je-Young Chang, Jerrod Peterson, Mark Carbone
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Publication number: 20190393165Abstract: Semiconductor packages and a method of forming a semiconductor package are described. The semiconductor package has a foundation layer, a conductive layer formed in the foundation layer, and a magnetic layer formed between the conductive and the foundation layer. The conductive layer and the magnetic layer are coupled to form a low-profile inductor shield. The semiconductor package also has a dielectric layer formed between the magnetic and foundation layer. The foundation layer is mounted between a motherboard and a semiconductor die, where the foundation layer is attached to the motherboard with solder balls. Accordingly, the low-profile inductor shield may include a z-height that is less than a z-height of the solder balls. The low-profile inductor shield may have solder pads that are coupled to the conductive layer. The foundation layer may include at least one of voltage regulator and inductor, where the inductor is located above the low-profile inductor shield.Type: ApplicationFiled: March 30, 2017Publication date: December 26, 2019Inventors: Kaladhar RADHAKRISHNAN, Jaejin LEE, Hao-Han HSU, Chung-Hao J. CHEN, Dong-Ho HAN
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Patent number: 10454163Abstract: Embodiments include apparatuses, methods, and systems including an electronic apparatus including an inductor within a circuit package affixed to a printed circuit board (PCB) having a ground layer, where the ground layer includes a mesh area that is substantially void along a contour of the inductor. An electronic apparatus may include a circuit package with an inductor, and a PCB, where the circuit package may be affixed to the PCB. The PCB may have a plurality of layers including a ground layer and a power layer, where the ground layer may be between the power layer and the inductor. The ground layer may include a mesh area that may be substantially void along a contour of the inductor within the circuit package. Other embodiments may also be described and claimed.Type: GrantFiled: September 22, 2017Date of Patent: October 22, 2019Assignee: Intel CorporationInventors: JaeJin Lee, Dong-Ho Han, Hao-Han Hsu
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Publication number: 20190311963Abstract: Techniques for fabricating a package substrate and/or a stiffener for a semiconductor package are described. For one technique, a package substrate comprises: a routing layer comprising a dielectric layer. A stiffener may be above the routing layer and a conductive line may be on the routing layer, the conductive line comprising first and second portions, the first portion having a first width, the second portion having a second width, the conductive line extending from a first region of the routing layer to a second region of the routing layer, the first region being under the stiffener, the second region being outside the stiffener, the first portion being on the first region, and the second portion being on the second region. One or more portions of the conductive line can be perpendicular to an edge of the stiffener. The perpendicular portion(s) may comprise a transition between the first and second widths.Type: ApplicationFiled: April 4, 2018Publication date: October 10, 2019Inventors: Stephen CHRISTIANSON, Stephen HALL, Emile DAVIES-VENN, Dong-Ho HAN, Kemal AYGUN, Konika GANGULY, Jun LIAO, M. Reza ZAMANI, Cory MASON, Kirankumar KAMISETTY
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Publication number: 20190304915Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate; a bridge, embedded in the package substrate, wherein the bridge includes an integral passive component, and wherein a surface of the bridge include first contacts in a first interconnect area and second contacts in a second interconnect area; a first die coupled to the passive component via the first contacts in the first interconnect area; and a second die coupled to the second contacts in the second interconnect area.Type: ApplicationFiled: June 20, 2019Publication date: October 3, 2019Applicant: Intel CorporationInventors: Amit Kumar Jain, Sameer Shekhar, Chin Lee Kuan, Kevin Joseph Doran, Dong-Ho Han
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Patent number: 10403581Abstract: Electronic device packages utilizing a stiffener coupled to a substrate with a magnetic lossy bonding layer to attenuate or absorb electromagnetic signals such as radio frequency interference (RFI) along with related systems and method are disclosed.Type: GrantFiled: September 29, 2017Date of Patent: September 3, 2019Assignee: Intel CorporationInventors: Jaejin Lee, Hao-Han Hsu, Chung-Hao J. Chen, Dong-Ho Han
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Publication number: 20190180929Abstract: An inductor includes a support member; a coil including a plurality of coil patterns disposed on one surface or the other surface of the support member, an insulating layer surrounding the coil, and an encapsulant encapsulating the support member and the coil patterns. At least portions of the insulating layer may be disposed to be recessed from the one surface or the other surface of the support member toward a center of the support member.Type: ApplicationFiled: July 10, 2018Publication date: June 13, 2019Inventors: Young Min HUR, Boum Seock KIM, Dong Ho HAN