Abstract: A display device includes a gate line and a data line aligned on a substrate, wherein the gate line and the data line cross each other to define a pixel area on the substrate, a gate electrode branching from the gate line, a source electrode branching from the data line on the gate electrode, a drain electrode spaced apart from the source electrode, a reflective electrode extending from the drain electrode, wherein the reflective electrode is formed in the pixel area, and an insulating layer pattern formed on the reflective electrode, wherein a protrusion pattern is provided at a surface of the insulating layer pattern.

Abstract: An array substrate includes a base substrate and a plurality of pixels on the base substrate. Each pixel includes a data line, first and second gate lines, first to third switching devices, and first and second pixel electrodes. The first and second gate lines cross the data line, and the second gate line is spaced apart from the first gate line. The first switching device is electrically connected to an adjacent gate line corresponding to an adjacent pixel. The second switching device is electrically connected to the data line and the first gate line. The third switching device is electrically connected to the data line and the second gate line. The first pixel electrode is electrically connected to the first and second switching devices, and the second pixel electrode is electrically connected to the first and third switching devices. The second pixel electrode is spaced apart from the first pixel electrode.

Abstract: Liquid crystal displays and fabrication methods thereof are provided. The liquid crystal display includes first substrate and second substrate facing the first substrate, and liquid crystal layer interposed therebetween. The first substrate includes a peripheral part spacer of which a surface includes a transparent conductive material, the peripheral part spacer being connected to a common voltage connector of the second substrate. A common voltage is applied to the first substrate through the common voltage connector and the peripheral part spacer. The peripheral part spacer is formed in the same process step with a display part spacer. To provide the peripheral part spacer with conductivity, the surface of the peripheral part spacer is covered with a transparent conductive material in the same process step in which the common electrode is formed on the first substrate.

Abstract: A polarizer assembly is provided. The polarizer assembly includes a polarizer, an adhesive layer on the polarizer, an adhesive layer protecting film that is attached to the adhesive layer and an antistatic member that absorbs an electrostatic charge generated during detachment of the adhesive layer protecting film from the adhesive layer.

Abstract: A chromeless photomask includes a main pattern portion and a complementary pattern portion formed in the surface of the transparent mask substrate adjacent to an outer peripheral edge of the main pattern portion. The main and complementary pattern portions are each formed by recessing a surface of a transparent mask substrate to produce respective protrusions and recesses that induce a phase difference of 180 degrees in light rays passing therethrough. The complementary pattern portion is designed to produce interference that prevents distortion in the photoresist pattern formed at a region by and corresponding to the edge of the main pattern portion of the photomask. Accordingly, the present invention provides for a relatively large secondary mask alignment margin.

Abstract: A method of repairing a thin film transistor array panel is provided. The thin film transistor array panel includes a gate line, a data line intersecting the gate line, a thin film transistor connected to the gate line and the data line and having a drain electrode, a pixel electrode including at least one first subpixel electrode connected to the drain electrode of the thin film transistor and a second subpixel electrode capacitively coupled to the at least one first subpixel electrode. The repairing method according to an embodiment of the present invention includes: disconnecting at least one of the second subpixel electrode and the at least one first subpixel electrode from the thin film transistor.

Abstract: The invention provides a LCD including an insulating substrate; a plurality of first signal lines formed on the insulating substrate; a plurality of second signal lines crossing and insulated from the first signal lines; a plurality of thin film transistors (TFT) coupled with the first and second signal lines; and a plurality of pixels including a plurality of first sub-pixel electrodes coupled with the TFTs and a plurality of second sub-pixel electrodes capacitively coupled with the first sub-pixel electrodes, wherein the pixels include a red (R) pixel, a green (G) pixel, and a blue (B) pixel and a voltage ratio or an area ratio of the second sub-pixel electrode with respect to the first sub-pixel electrode is different among the R, G, and B pixels to improve a brightness ratio of R, G, and B components at a lateral position.

Abstract: A mask and a method of forming the mask obviate optical proximity effects. The mask includes a light-shielding layer on a transparent substrate. The light-shielding layer is patterned to form a main pattern and a phantom pattern. The main and phantom patterns each have a light shielding portion and a light-transmitting portion. The pitch of the features constituting the phantom pattern is identical to the pitch of the features constituting the main pattern. The shape of the light-transmitting features of the phantom pattern region is identical to the shape of the light-transmitting features of the main pattern region.

Abstract: A chromeless photomask includes a main pattern portion and a complementary pattern portion formed in the surface of the transparent mask substrate adjacent to an outer peripheral edge of the main pattern portion. The main pattern and complementary portions are each formed by recessing a surface of a transparent mask substrate to produce respective protrusions and recesses that induce a phase difference of 180 degrees in light rays passing therethrough. The complementary pattern portion is designed to produce interference that prevents distortion in the photoresist pattern formed at a region by and corresponding to the edge of the main pattern portion of the photomask. Accordingly, the present invention provides for a relatively large secondary mask alignment margin.

Abstract: A method for forming alignment keys on the scribe line areas of a semiconductor wafer. An etch blocking layer is used to reduce the depth of the channels forming the alignment key. One of the layers of material deposited on the semiconductor wafer to form integrated circuit devices on the wafer may be used as the etch blocking layer. A portion of this layer of material may be left intact on the scribe line areas during the manufacturing process. The subsequently deposited layers have an etch selectivity with respect to the etch blocking layer and the subsequently deposited layers are etched down to the etch blocking layer to form the alignment keys.

Abstract: A method for forming alignment keys on the scribe line areas of a semiconductor wafer. An etch blocking layer is used to reduce the depth of the channels forming the alignment key. One of the layers of material deposited on the semiconductor wafer to form integrated circuit devices on the wafer may be used as the etch blocking layer. A portion of this layer of material may be left intact on the scribe line areas during the manufacturing process. The subsequently deposited layers have an etch selectivity with respect to the etch blocking layer and the subsequently deposited layers are etched down to the etch blocking layer to form the alignment keys.

Abstract: A method for forming alignment keys on the scribe line areas of a semiconductor wafer. An etch blocking layer is used to reduce the depth of the channels forming the alignment key. One of the layers of material deposited on the semiconductor wafer to form integrated circuit devices on the wafer may be used as the etch blocking layer. A portion of this layer of material may be left intact on the scribe line areas during the manufacturing process. The subsequently deposited layers have an etch selectivity with respect to the etch blocking layer and the subsequently deposited layers are etched down to the etch blocking layer to form the alignment keys.

Abstract: The present invention relates to a novel genipin derivative represented by formula (I), which has anti hepatitis B virus (HBV) activity, in which R.sub.1 represents lower alkyl, benzyl, etc., R.sub.2 represents hydroxymethyl, formyl, acetyl, etc., R.sub.3 represents methoxycarbonyl, formyl, etc., its pharmaceutically acceptable salt, and stereoisomer.