Abstract: Tasks associated with users can be managed for efficient workflow management. A task management component (TMC) can analyze, including performing artificial intelligence-based analysis on, task-related information relating to associated with a user(s), assessment information relating to assessing performance or expertise associated with a task, biometric information relating to health, diet, and activity associated with the user(s), and/or user(s) feedback information. Based on the analysis, TMC can adaptively adjust respective attributes associated with respective tasks, resulting in respective adjusted attributes associated with the respective tasks. Based on the respective adjusted attributes, TMC can determine task information and can present the task information to a device(s) associated with the user(s) to facilitate performance of the tasks.

Abstract: A disclosed apparatus may include at least one touch sensor and an integrated film that includes at least one antenna, wherein the integrated film is at least partially disposed on the at least one touch sensor such that the at least one touch sensor operates as a radiating element for the at least one antenna. Various other apparatuses, systems, and methods are also disclosed.

Abstract: The disclosed devices and systems may include transparent antennas and touch displays that may be included in wearable devices. An example wearable device may include a display module including a display stack, the display stack including a display cover layer, an antenna layer, and a display layer, wherein the antenna layer (1) is positioned between the display cover layer and the display layer, and (2) includes at least one antenna element. Various other systems and devices are disclosed.

Abstract: The present disclosure provides an integrated circuit structure that includes a semiconductor substrate having a first region and a second region having an area less than about 10 micron×10 micron; a first material layer over the semiconductor substrate and patterned to have a first circuit feature in the first region and a first mark in the second region; and a second material layer over the first material layer and patterned to have a second circuit feature in the first region and a second mark in the second region. The first mark includes first mark features oriented in a first direction, and second mark features oriented in a second direction perpendicular to the first direction. The second mark includes third mark features oriented in the first direction, and fourth mark features oriented in the second direction.

Abstract: A method of exposing a wafer substrate includes receiving an integrated circuit (IC) design layout defining a pattern; determining a temperature profile of a mask based on the IC design layout, the pattern being formed on the mask; calculating a pre-corrected overlay shift for the mask based on the calculated temperature profile; and exposing a resist layer coated on a substrate using the mask with overlay compensation based on the pre-corrected overlay shift.

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a main feature; performing an optical proximity correction (OPC) process to the design layout; and thereafter, performing a jog reduction process to the design layout such that jog features of the design layout are reduced.

Abstract: A method of exposing a wafer substrate includes receiving an integrated circuit (IC) design layout defining a pattern; determining a temperature profile of a mask based on the IC design layout, the pattern being formed on the mask; calculating a pre-corrected overlay shift for the mask based on the calculated temperature profile; and exposing a resist layer coated on a substrate using the mask with overlay compensation based on the pre-corrected overlay shift.

Abstract: A method of assigning layout patterns includes identifying a first set of layout patterns of a current layout design that is new or has been modified in comparison with a reference layout design. A second set of layout patterns of the current layout design is identified. A member of the second set of layout patterns that is not a member of the first set of layout patterns has a distance, less than a predetermined threshold distance, to at least another member of the second set of layout patterns. A third set of layout patterns is not modified in comparison with the reference layout design. The third set of layout patterns is assigned to a plurality of masks according to the reference pattern-assigning result.

Abstract: A method of assigning layout patterns includes identifying a first set of layout patterns of a current layout design that is new or has been modified in comparison with a reference layout design. A second set of layout patterns of the current layout design is identified. A member of the second set of layout patterns that is not a member of the first set of layout patterns has a distance, less than a predetermined threshold distance, to at least another member of the second set of layout patterns. A third set of layout patterns is not modified in comparison with the reference layout design. The third set of layout patterns is assigned to a plurality of masks according to the reference pattern-assigning result.

Abstract: A method of exposing a wafer substrate includes receiving an integrated circuit (IC) design layout defining a pattern; determining a temperature profile of a mask based on the IC design layout, the pattern being formed on the mask; calculating a pre-corrected overlay shift for the mask based on the calculated temperature profile; and exposing a resist layer coated on a substrate using the mask with overlay compensation based on the pre-corrected overlay shift.

Abstract: The present disclosure provides an integrated circuit structure that includes a semiconductor substrate having a first region and a second region having an area less than about 10 micron×10 micron; a first material layer over the semiconductor substrate and patterned to have a first circuit feature in the first region and a first mark in the second region; and a second material layer over the first material layer and patterned to have a second circuit feature in the first region and a second mark in the second region. The first mark includes first mark features oriented in a first direction, and second mark features oriented in a second direction perpendicular to the first direction. The second mark includes third mark features oriented in the first direction, and fourth mark features oriented in the second direction.

Abstract: The present disclosure provides an integrated circuit structure that includes a semiconductor substrate having a first region and a second region having an area less than about 10 micron×10 micron; a first material layer over the semiconductor substrate and patterned to have a first circuit feature in the first region and a first mark in the second region; and a second material layer over the first material layer and patterned to have a second circuit feature in the first region and a second mark in the second region. The first mark includes first mark features oriented in a first direction, and second mark features oriented in a second direction perpendicular to the first direction. The second mark includes third mark features oriented in the first direction, and fourth mark features oriented in the second direction.

Abstract: The present disclosure provides for many different embodiments. A mask fabrication method and system is provided. The method and system identify critical areas of an integrated circuit (IC) design layout that has undergone optical proximity correction. The critical areas are areas of the OPCed IC design layout that are at risk for hot spots. A lithography process check is then performed on the critical areas of the OPCed IC design layout.

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a main feature; performing an optical proximity correction (OPC) process to the design layout; and thereafter, performing a jog reduction process to the design layout such that jog features of the design layout are reduced.

Abstract: A method of making a mask includes receiving an IC design layout from a designer, applying an logic operation (LOP) correction, performing an OPC correction, fracturing the modified data into a plurality of main features in an electron beam format, and sending the electron beam format data to a mask writer for a mask fabrication. An XOR operation is implemented into the method to check and verify if a pattern is lost during OPC modification and/or data fracture. A BACKBONE XOR operation is also implemented into the method for a plurality of main features with a critical dimension (CD) size smaller than the max OPC correction to check and verify if a small pattern feature is lost during OPC modification and/or data fracture for 45 nm and beyond semiconductor technologies.

Abstract: A method of making a mask includes receiving an IC design layout from a designer, applying an logic operation (LOP) correction, performing an OPC correction, fracturing the modified data into a plurality of main features in an electron beam format, and sending the electron beam format data to a mask writer for a mask fabrication. An XOR operation is implemented into the method to check and verify if a pattern is lost during OPC modification and/or data fracture. A BACKBONE XOR operation is also implemented into the method for a plurality of main features with a critical dimension (CD) size smaller than the max OPC correction to check and verify if a small pattern feature is lost during OPC modification and/or data fracture for 45 nm and beyond semiconductor technologies.

Abstract: The present disclosure provides an integrated circuit structure that includes a semiconductor substrate having a first region and a second region having an area less than about 10 micron×10 micron; a first material layer over the semiconductor substrate and patterned to have a first circuit feature in the first region and a first mark in the second region; and a second material layer over the first material layer and patterned to have a second circuit feature in the first region and a second mark in the second region. The first mark includes first mark features oriented in a first direction, and second mark features oriented in a second direction perpendicular to the first direction. The second mark includes third mark features oriented in the first direction, and fourth mark features oriented in the second direction.

Abstract: The present disclosure provides for methods of reducing cycle time in data preparation. In one embodiment, a method includes receiving an initial integrated circuit (IC) design layout and an optical proximity correction (OPC)-processed initial IC design layout, and receiving a revised IC design layout. The method further includes comparing the revised IC design layout to the initial IC design layout to identify a difference region of the revised IC design layout from the initial IC design layout, performing an OPC on the difference region of the revised IC design layout, and merging the OPC-processed difference region of the revised IC design layout with the OPC-processed initial IC design layout.

Abstract: The present disclosure provides for methods of reducing cycle time in data preparation. In one embodiment, a method includes receiving an initial integrated circuit (IC) design layout and an optical proximity correction (OPC)-processed initial IC design layout, and receiving a revised IC design layout. The method further includes comparing the revised IC design layout to the initial IC design layout to identify a difference region of the revised IC design layout from the initial IC design layout, performing an OPC on the difference region of the revised IC design layout, and merging the OPC-processed difference region of the revised IC design layout with the OPC-processed initial IC design layout.

Abstract: Provided is a photomask that includes a substrate having a first region and a second region, a first pattern disposed in the first region of the substrate, and a second pattern disposed in the second region of the substrate. The first and second patterns are a decomposition of a design pattern to be transferred onto a wafer in a lithography process.