Abstract: The present disclosure provides a display panel. The display panel includes a base substrate, a first conductive layer and an active layer that are stacked in sequence. The first conductive layer includes a plurality of gate signal lines. The gate signal line includes a body part and a plurality of additional parts. An orthographic projection of the body part on the base substrate extends along a first direction. The plurality of additional parts are distributed at intervals in the first direction and coupled to a side of the body part in a second direction. The additional part is used to form a gate of a driving transistor. The active layer includes a plurality of active structures disposed corresponding to the plurality of additional parts. Orthographic projections of the plurality of active structures on the base substrate are separated from each other.

Abstract: The present invention relates to a method and system for actively adjusting diopter of a head-mounted display, and a head-mounted display. The method includes the following steps: adjusting a relative distance between a displaying component of the head-mounted display and an optical component by a motor driving component; presetting a mapping relationship between a diopter value and a motor pulse number; accordingly converting into a control signal for the motor driving component according to the mapping relationship; and actively adjusting the relative distance between the displaying component of the head-mounted display and the optical component by the motor driving component according to the control signal. A target diopter value is inputted and converted into a corresponding control signal. The motor driving component actively adjusts the relative distance between the displaying component of the head-mounted display and the optical component according to the control signal.

Abstract: The present disclosure provides a semiconductor structure and a method for forming the semiconductor structure. The method includes: providing a substrate including a device region and a guard ring region surrounding the device region; and forming a power device in the device region and forming a guard ring in the guard ring region, wherein the guard ring is doped with a first dopant ion that is formed by a partial doping process used in a formation of the power device, and a conductivity type of the first dopant ion in the guard ring is different from a device type of the power device. Since the guard ring is formed by the necessary doping process used in forming the power device, additional photomask process and doping process for forming the guard ring is omitted, effectively reducing process steps and process costs.

Abstract: Provided is a method for treating diseases related to cardiac tissue damage or cardiac insufficiency in a subject. The method includes the step of locally applying a mesenchymal stem cell sheet such as an umbilical cord mesenchymal stem cell sheet to the heart of the subject. Also provided are related use and compositions of the mesenchymal stem cell sheet.

Abstract: A method for cryopreserving cells, a cell cryopreservation solution and a composition are provided. The method includes: providing a suspension for the cells to be cryopreserved in a cell cryopreservation solution; and cryopreserving the suspension. The cell cryopreservation solution includes dimethyl sulfoxide, plasma, citric acid, sodium citrate, potassium dihydrogen phosphate or sodium dihydrogen phosphate, glucose and adenine.

Abstract: A transfer device includes a transfer device body, the transfer device body includes a carrying plate and a picking-up plate. The picking-up plate is configured to drive the carrying plate to move, and a first end of the picking-up plate is fixedly connected to a first edge portion of the carrying plate. The carrying plate is configured to pick up and carry an object to be transplanted.

Abstract: A head-mounted display apparatus is disclosed which including a main frame arranged with left and right display screens, left and right eyepieces arranged in correspondence with the left and right display screen. The main frame is further arranged with a diopter and interpupillary distance adjustment mechanism for adjusting a distance between the display screens and the eyepieces and a distance between two eyepieces at each side. The diopter and interpupillary distance adjustment mechanism employs a rotation operation and a sliding operation of a same knob assembly for achieving adjustments of a diopter and an interpupillary distance of the head-mounted display apparatus. That is, not only the operation is easier, but also the product structure is simplified, so that the head-mounted display apparatus has a more compact structure, lighter weight and more comfortable and convenient use.

Abstract: A head-mounted display apparatus is disclosed which including a main frame arranged with left and right display screens, left and right eyepieces arranged in correspondence with the left and right display screen. The main frame is further arranged with a diopter and interpupillary distance adjustment mechanism for adjusting a distance between the display screens and the eyepieces and a distance between two eyepieces at each side. The diopter and interpupillary distance adjustment mechanism employs a rotation operation and a sliding operation of a same knob assembly for achieving adjustments of a diopter and an interpupillary distance of the head-mounted display apparatus. That is, not only the operation is easier, but also the product structure is simplified, so that the head-mounted display apparatus has a more compact structure, lighter weight and more comfortable and convenient use.

Abstract: An NLDMOS device that includes a drift region, a P well, and a first PTOP layer and a second PTOP layer formed on the drift region, wherein the first PTOP layer has the same lateral size with the second PTOP layer, the first PTOP layer is spaced from the second PTOP layer in the longitudinal direction and located on the bottom of the second PTOP layer, with the depth of the first PTOP layer less than or equal to that of the bottom of the P well. The present invention also discloses a method for manufacturing the NLDMOS device.

Abstract: An NLDMOS device that includes a drift region, a P well, and a first PTOP layer and a second PTOP layer formed on the drift region, wherein the first PTOP layer has the same lateral size with the second PTOP layer, the first PTOP layer is spaced from the second PTOP layer in the longitudinal direction and located on the bottom of the second PTOP layer, with the depth of the first PTOP layer less than or equal to that of the bottom of the P well. The present invention also discloses a method for manufacturing the NLDMOS device.

Abstract: An isolation NLDMOS device including: an N well and a P well adjacent to each other on an upper part of a P substrate; on the upper part of the P well are sequentially arranged a first P type heavily doped region, a first field oxide, and a second P type heavily doped region; on the upper part of the N well are arranged a second field oxide and an N type heavily doped region; a gate oxide is between the second P type heavily doped region and the second field oxide; a gate polysilicon sits above the gate oxide and part of the second field oxide; from the first P type heavily doped region, the second P type heavily doped region and the N type heavily doped region are led out each a connecting wire via a respective contact hole.

Abstract: An isolation NLDMOS device including: an N well and a P well adjacent to each other on an upper part of a P substrate; on the upper part of the P well are sequentially arranged a first P type heavily doped region, a first field oxide, and a second P type heavily doped region; on the upper part of the N well are arranged a second field oxide and an N type heavily doped region; a gate oxide is between the second P type heavily doped region and the second field oxide; a gate polysilicon sits above the gate oxide and part of the second field oxide; from the first P type heavily doped region, the second P type heavily doped region and the N type heavily doped region are led out each a connecting wire via a respective contact hole.

Abstract: A SiGe HBT is disclosed, which includes: a silicon substrate; shallow trench field oxides formed in the silicon substrate; a pseudo buried layer formed at bottom of each shallow trench field oxide; a collector region formed beneath the surface of the silicon substrate, the collector region being sandwiched between the shallow trench field oxides and between the pseudo buried layers; a polysilicon gate formed above each shallow trench field oxide having a thickness of greater than 150 nm; a base region on the polysilicon gates and the collector region; emitter region isolation oxides on the base region; and an emitter region on the emitter region isolation oxides and a part of the base region. The polysilicon gate is formed by gate polysilicon process of a MOSFET in a CMOS process. A method of manufacturing the SiGe HBT is also disclosed.

Abstract: A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) is disclosed, including: a substrate; two field oxide regions formed in the substrate; two pseudo buried layers, each being formed under a corresponding one of the field oxide regions; a collector region formed between the field oxide regions, the collector region laterally extending under a corresponding one of the field oxide regions and each side of the collector region being connected with a corresponding one of the pseudo buried layers; a matching layer formed under both the pseudo buried layers and the collector region; and two deep hole electrodes, each being formed in a corresponding one of the field oxide regions, the deep hole electrodes being connected to the corresponding ones of the pseudo buried layers for picking up the collector region. A manufacturing method of the SiGe HBT is also disclosed.

Abstract: A zener diode in a SiGe BiCMOS process is disclosed. An N-type region of the zener diode is formed in an active region and surrounded by an N-deep well. A pseudo buried layer is formed under each of the shallow trench field oxide regions on a corresponding side of the active region, and the N-type region is connected to the pseudo buried layers via the N-deep well. The N-type region has its electrode picked up by deep hole contacts. A P-type region of the zener diode is formed of a P-type ion implanted region in the active region. The P-type region is situated above and in contact with the N-type region, and has a doping concentration greater than that of the N-type region. The P-type region has its electrode picked up by metal contact. A method of fabricating zener diode in a SiGe BiCMOS process is also disclosed.

Abstract: A high-speed SiGe HBT is disclosed, which includes: a substrate; STIs formed in the substrate; a collector region formed beneath the substrate surface and located between the STIs; an epitaxial dielectric layer including two portions, one being located on the collector region, the other being located on one of the STIs; a base region formed both in a region between and on surfaces of the two portions of the epitaxial dielectric layer; an emitter dielectric layer including two portions, both portions being formed on the base region; an emitter region formed both in a region between and on surfaces of the two portions of the emitter dielectric layer; a contact hole formed on a surface of each of the base region, the emitter region and the collector region. A method of manufacturing high-speed SiGe HBT is also disclosed.

Abstract: A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) device that includes a substrate; a buried oxide layer near a bottom of the substrate; a collector region above and in contact with the buried oxide layer; a field oxide region on each side of the collector region; a pseudo buried layer under each field oxide region and in contact with the collector region; and a through region under and in contact with the buried oxide layer. A method for manufacturing a SiGe HBT device is also disclosed. The SiGe HBT device can isolate noise from the bottom portion of the substrate and hence can improve the intrinsic noise performance of the device at high frequencies.

Abstract: An ultra-high voltage silicon-germanium (SiGe) heterojunction bipolar transistor (HBT), which includes: a P-type substrate; an N-type matching layer, a P-type matching layer and an N? collector region stacked on the P-type substrate from bottom up; two field oxide regions separately formed in the N? collector region; N+ pseudo buried layers, each under a corresponding one of the field oxide regions and in contact with each of the N-type matching layer, the P-type matching layer and the N? collector region; an N+ collector region between the two field oxide regions and through the N? collector region and the P-type matching layer and extending into the N-type matching layer; and deep hole electrodes, each in a corresponding one of the field oxide regions and in contact with a corresponding one of the N+ pseudo buried layers. A method of fabricating an ultra-high voltage SiGe HBT is also disclosed.

Abstract: An ultra high voltage silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) is disclosed, in which, a collector region is formed between two isolation structures; a pseudo buried layer is formed under each isolation structure and each side of the collector region is connected with a corresponding pseudo buried layer; a SiGe field plate is formed on each of the isolation structures; each pseudo buried layer is picked up by a first contact hole electrode and each SiGe field plate is picked up by a second contact hole electrode; and each first contact hole electrode is connected to its adjacent second contact hole electrode and the two contact hole electrodes jointly serve as an emitter. A manufacturing method of the ultra high voltage SiGe HBT is also disclosed.

Abstract: A high-speed SiGe HBT is disclosed, which includes: a substrate; STIs formed in the substrate; a collector region formed beneath the substrate surface and located between the STIs; an epitaxial dielectric layer including two portions, one being located on the collector region, the other being located on one of the STIs; a base region formed both in a region between and on surfaces of the two portions of the epitaxial dielectric layer; an emitter dielectric layer including two portions, both portions being formed on the base region; an emitter region formed both in a region between and on surfaces of the two portions of the emitter dielectric layer; a contact hole formed on a surface of each of the base region, the emitter region and the collector region. A method of manufacturing high-speed SiGe HBT is also disclosed.