Abstract: The invention discloses a vertical parasitic PNP transistor in a BiCMOS process and manufacturing method of the same, wherein an active region is isolated by STIs. The transistor includes a collector region, a base region, an emitter region, pseudo buried layers, and N-type polysilicon. The pseudo buried layers, formed at the bottom of the STIs located on both sides of the collector region, extend laterally into the active region and contact with the collector region, whose electrodes are picked up through making deep-hole contacts in the STIs. The N-type polysilicon is formed on the base region and contacts with it, whose electrodes are picked up through making metal contacts on the N-type polysilicon. The transistors can be used as output devices in high-speed and high-gain circuits, efficiently reducing the transistors area, diminishing the collector resistance, and improving the transistors performance. The method can reduce the cost without additional technological conditions.

Abstract: An ultra-high voltage silicon-germanium (SiGe) heterojunction bipolar transistor (HBT), which includes: a P-type substrate; an N-type matching layer, a P-type matching layer and an N? collector region stacked on the P-type substrate from bottom up; two field oxide regions separately formed in the N? collector region; N+ pseudo buried layers, each under a corresponding one of the field oxide regions and in contact with each of the N-type matching layer, the P-type matching layer and the N? collector region; an N+ collector region between the two field oxide regions and through the N? collector region and the P-type matching layer and extending into the N-type matching layer; and deep hole electrodes, each in a corresponding one of the field oxide regions and in contact with a corresponding one of the N+ pseudo buried layers. A method of fabricating an ultra-high voltage SiGe HBT is also disclosed.

Abstract: A parasitic vertical PNP bipolar transistor in BiCMOS process comprises a collector, a base and an emitter. The collector is formed by active region with p-type ion implanting layer (P type well in NMOS). It connects a P-type conductive region, which formed in the bottom region of shallow trench isolation (STI). The collector terminal connection is through the P-type buried layer and the adjacent active region. The base is formed by N type ion implanting layer above the collector which shares a N-type lightly doped drain (NLDD) implanting of NMOS. Its connection is through the N-type poly on the base region. The emitter is formed by the P-type epitaxy layer on the base region with heavy p-type doped, and connected by the extrinsic base region of NPN bipolar transistor device. This invention also includes the fabrication method of this parasitic vertical PNP bipolar transistor in BiCMOS process.

Abstract: The present invention discloses a pseudo buried layer, a deep hole contact and a bipolar transistor, and also discloses a manufacturing method of a pseudo buried layer, including: etching a silicon substrate to form an active region and shallow trenches; sequentially implanting phosphorous ion and arsenic ion into the bottom of the shallow trenches to form phosphorus impurity regions and arsenic impurity regions; conducting thermal annealing to the phosphorus impurity regions and arsenic impurity regions. The implantation of the pseudo buried layer, adopting phosphorous with rapid thermal diffusion and arsenic with slow thermal diffusion, can improve the impurity concentration on the surface of the pseudo buried layers, reduce the sheet resistance of the pseudo buried layer, form a good ohmic contact between the pseudo buried layer and a deep hole and reduce the contact resistance, and improve the frequency characteristic and current output of triode devices.

Abstract: A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) device that includes a substrate; a buried oxide layer near a bottom of the substrate; a collector region above and in contact with the buried oxide layer; a field oxide region on each side of the collector region; a pseudo buried layer under each field oxide region and in contact with the collector region; and a through region under and in contact with the buried oxide layer. A method for manufacturing a SiGe HBT device is also disclosed. The SiGe HBT device can isolate noise from the bottom portion of the substrate and hence can improve the intrinsic noise performance of the device at high frequencies.

Abstract: A parasitic PNP bipolar transistor, wherein a base region includes a first and a second region; the first region is formed in an active area, has a depth larger than shallow trench field oxides, and has its bottom laterally extended into the bottom of the shallow trench field oxides on both sides of an active area; the second region is formed in an upper part of the first region and has a higher doping concentration; an N-type and a P-type pseudo buried layer is respectively formed at the bottom of the shallow trench field oxides; a deep hole contact is formed on top of the N-type pseudo buried layer to pick up the base; the P-type pseudo buried layer forms a collector region separated from the active area by a lateral distance; an emitter region is formed by a P-type SiGe epitaxial layer formed on top of the active area.

Abstract: A SiGe HBT is disclosed, which includes: a silicon substrate; shallow trench field oxides formed in the silicon substrate; a pseudo buried layer formed at bottom of each shallow trench field oxide; a collector region formed beneath the surface of the silicon substrate, the collector region being sandwiched between the shallow trench field oxides and between the pseudo buried layers; a polysilicon gate formed above each shallow trench field oxide having a thickness of greater than 150 nm; a base region on the polysilicon gates and the collector region; emitter region isolation oxides on the base region; and an emitter region on the emitter region isolation oxides and a part of the base region. The polysilicon gate is formed by gate polysilicon process of a MOSFET in a CMOS process. A method of manufacturing the SiGe HBT is also disclosed.

Abstract: A PIS capacitor in a SiGe HBT process is disclosed, wherein the PIS capacitor includes: a silicon substrate; a P-well and shallow trench isolations formed in the silicon substrate; a P-type heavily doped region formed in an upper portion of the P-well; an oxide layer and a SiGe epitaxial layer formed above the P-type heavily doped region; spacers formed on sidewalls of the oxide layer and the SiGe epitaxial layer; and contact holes for picking up the P-well and the SiGe epitaxial layer and connecting each of the P-well and the SiGe epitaxial layer to a metal wire. A method of manufacturing the PIS capacitor is also disclosed. The PIS capacitor of the present invention is manufactured by using SiGe HBT process, thus providing one more device option for the SiGe HBT process.

Abstract: A SiGe HBT having a position controlled emitter-base junction is disclosed. The SiGe HBT includes: a collector region formed of an N-doped active region; a base region formed on the collector region and including a base epitaxial layer, the base epitaxial layer including a SiGe layer and a capping layer formed thereon, the SiGe layer being formed of a SiGe epitaxial layer doped with a P-type impurity, the capping layer being doped with an N-type impurity; and an emitter region formed on the base region, the emitter region being formed of polysilicon. By optimizing the distribution of impurities doped in the base region, a controllable position of the emitter-base junction and adjustability of the reverse withstanding voltage thereof can be achieved, and thereby increasing the stability of the process and improving the uniformity within wafer.

Abstract: This invention published a parasitic vertical PNP bipolar transistor in BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process; the bipolar transistor comprises a collector, a base and an emitter. Collector is formed by active region with p-type ion implanting layer. It connects a p-type buried layer which formed in the bottom region of STI (Shallow Trench Isolation). The collector terminal connection is through the p-type buried layer and the adjacent active region. The base is formed by active region with n type ion implanting which is on the collector. Its connection is through the original p-type epitaxy layer after converting to n-type. The emitter is formed by the p-type epitaxy layer on the base region with heavy p-type doped. This invention also comprises the fabrication method of this parasitic vertical PNP bipolar in BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process.

Abstract: A parasitic vertical PNP device in one type of BiCMOS process with shallow trench isolation (STI) comprises a collector formed by a p type impurity ion implantation layer inside active area, the bottom of collector connects to a p type buried layer, the p type pseudo buried layer is formed in bottom of shallow trench at both sides of collector active region through ion implantation, deep contacts through field oxide to connect pseudo buried layers and to pick up the collector; a base, formed by n type impurity ion implantation layer which sits on top of above stated collector; an emitter, a p type epitaxy layer lies above base and is connected out directly by a metal contact. Part of the p type epitaxy layer is converted into n type, which serves as connection path of base. Present invented PNP can be used as output device of BiCMOS high frequency circuit. It has a small device area and conduction resistance.

Abstract: A SiGe HBT is disclosed. A collector region consists of a first ion implantation region in an active area as well as second and third ion implantation regions respectively at bottom of field oxide regions. Each third ion implantation region has a width smaller than that of the field oxide region, has one side connected to first ion implantation region and has second side connected to a pseudo buried layer; each second ion implantation region located at bottom of the third ion implantation region and pseudo buried layer is connected to them and has a width equal to that of the field oxide region. Third ion implantation region has a higher doping concentration and a smaller junction depth than those of first and second ion implantation regions. Deep hole contacts are formed on top of pseudo buried layers in field oxide regions to pick up collector region.

Abstract: A SiGe HBT is disclosed. A collector region consists of a first ion implantation region in an active area as well as second and third ion implantation regions respectively at bottom of field oxide regions. Each third ion implantation region has a width smaller than that of the field oxide region, has one side connected to first ion implantation region and has second side connected to a pseudo buried layer; each second ion implantation region located at bottom of the third ion implantation region and pseudo buried layer is connected to them and has a width equal to that of the field oxide region. Third ion implantation region has a higher doping concentration and a smaller junction depth than those of first and second ion implantation regions. Deep hole contacts are formed on top of pseudo buried layers in field oxide regions to pick up collector region.

Abstract: A parasitic PNP bipolar transistor, wherein a base region includes a first and a second region; the first region is formed in an active area, has a depth larger than shallow trench field oxides, and has its bottom laterally extended into the bottom of the shallow trench field oxides on both sides of an active area; the second region is formed in an upper part of the first region and has a higher doping concentration; an N-type and a P-type pseudo buried layer is respectively formed at the bottom of the shallow trench field oxides; a deep hole contact is formed on top of the N-type pseudo buried layer to pick up the base; the P-type pseudo buried layer forms a collector region separated from the active area by a lateral distance; an emitter region is formed by a P-type SiGe epitaxial layer formed on top of the active area.

Abstract: The present invention discloses a pseudo buried layer, a deep hole contact and a bipolar transistor, and also discloses a manufacturing method of a pseudo buried layer, including: etching a silicon substrate to form an active region and shallow trenches; sequentially implanting phosphorous ion and arsenic ion into the bottom of the shallow trenches to form phosphorus impurity regions and arsenic impurity regions; conducting thermal annealing to the phosphorus impurity regions and arsenic impurity regions. The implantation of the pseudo buried layer, adopting phosphorous with rapid thermal diffusion and arsenic with slow thermal diffusion, can improve the impurity concentration on the surface of the pseudo buried layers, reduce the sheet resistance of the pseudo buried layer, form a good ohmic contact between the pseudo buried layer and a deep hole and reduce the contact resistance, and improve the frequency characteristic and current output of triode devices.

Abstract: The invention discloses a vertical parasitic PNP transistor in a BiCMOS process and manufacturing method of the same, wherein an active region is isolated by STIs. The transistor includes a collector region, a base region, an emitter region, pseudo buried layers, and N-type polysilicon. The pseudo buried layers, formed at the bottom of the STIs located on both sides of the collector region, extend laterally into the active region and contact with the collector region, whose electrodes are picked up through making deep-hole contacts in the STIs. The N-type polysilicon is formed on the base region and contacts with it, whose electrodes are picked up through making metal contacts on the N-type polysilicon. The transistors can be used as output devices in high-speed and high-gain circuits, efficiently reducing the transistors area, diminishing the collector resistance, and improving the transistors performance. The method can reduce the cost without additional technological conditions.

Abstract: This invention published a parasitic vertical PNP bipolar transistor in BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process; the bipolar transistor comprises a collector, a base and an emitter. Collector is formed by active region with p-type ion implanting layer. It connects a p-type buried layer which formed in the bottom region of STI (Shallow Trench Isolation). The collector terminal connection is through the p-type buried layer and the adjacent active region. The base is formed by active region with n type ion implanting which is on the collector. Its connection is through the original p-type epitaxy layer after converting to n-type. The emitter is formed by the p-type epitaxy layer on the base region with heavy p-type doped. This invention also comprises the fabrication method of this parasitic vertical PNP bipolar in BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process.

Abstract: A parasitic vertical PNP device in one type of BiCMOS process with shallow trench isolation (STI) comprises a collector formed by a p type impurity ion implantation layer inside active area, the bottom of collector connects to a p type buried layer, the p type pseudo buried layer is formed in bottom of shallow trench at both sides of collector active region through ion implantation, deep contacts through field oxide to connect pseudo buried layers and to pick up the collector; a base, formed by n type impurity ion implantation layer which sits on top of above stated collector; an emitter, a p type epitaxy layer lies above base and is connected out directly by a metal contact. Part of the p type epitaxy layer is converted into n type, which serves as connection path of base. Present invented PNP can be used as output device of BiCMOS high frequency circuit. It has a small device area and conduction resistance.

Abstract: A parasitic vertical PNP bipolar transistor in BiCMOS process comprises a collector, a base and an emitter. The collector is formed by active region with p-type ion implanting layer (P type well in NMOS). It connects a P-type conductive region, which formed in the bottom region of shallow trench isolation (STI). The collector terminal connection is through the P-type buried layer and the adjacent active region. The base is formed by N type ion implanting layer above the collector which shares a N-type lightly doped drain (NLDD) implanting of NMOS. Its connection is through the N-type poly on the base region. The emitter is formed by the P-type epitaxy layer on the base region with heavy p-type doped, and connected by the extrinsic base region of NPN bipolar transistor device. This invention also includes the fabrication method of this parasitic vertical PNP bipolar transistor in BiCMOS process.

Abstract: A high voltage bipolar transistor with shallow trench isolation (STI) comprises the areas of a collector formed by implanting first electric type impurities into active area and connected with pseudo buried layers at two sides; Pseudo buried layers which are formed by implanting high dose first type impurity through the bottoms of STI at two sides if active area, and do not touch directly; deep contact through field oxide to contact pseudo buried layers and pick up the collectors; a base deposited on the collector by epitaxial growth and in-situ doped by second electric type impurity, in which the intrinsic base touches local collector and extrinsic base is used for base pick-up; a emitter which is a polysilicon layer deposited on the intrinsic base and doped with first electric type impurities. This invention makes the depletion region of collector/base junction from 1D (vertical) distribution to 2D (vertical and lateral) distribution.