Abstract: A method is provided for operating a nonvolatile memory comprising memory cells stacked on a substrate. The method comprises counting a number of program loops performed in a first program operation of selected memory cells connected to a selected wordline, and controlling an increment of a program voltage between successive program loops of a second program operation of the selected memory cells according to the counted number.

Abstract: The present invention relates to a method for recycling artificial grass containing fibrous material, and comprises: a supplying step for supplying the artificial grass comprising a base material, and a yarn; a separation step for separating the filler from the artificial grass yarn and the base material; and a crushing step for crushing the yarn and the base material of the artificial grass from which the filler is separated; and a reconstruction step for forming the artificial grass yarn and the base material that are crushed into recycled material. As a result, provided is the method for recycling the artificial grass containing the fibrous material, which can completely separate the filler and foreign material from the base material and the yarn that comprise the artificial grass and recycle the artificial grass yarn, base material, and the filler, thereby preventing environmental pollution.

Abstract: In method of programming a nonvolatile memory device including a plurality of multi-level cells that store multi-bit data according to example embodiments, a least significant bit (LSB) program operation is performed to program LSBs of the multi-bit data in the plurality of multi-level cells. A most significant bit (MSB) program operation is performed to program MSBs of the multi-bit data in the plurality of multi-level cells. To perform the MSB program, an MSB pre-program operation is performed on first multi-level cells, from among the plurality of multi-level cells, that are to be programmed to a highest target program state among a plurality of target program states, and an MSB main program operation is performed to program the plurality of multi-level cells to the plurality of target program states corresponding to the multi-bit data.

Abstract: According to example embodiments, a nonvolatile memory device includes a memory cell array including a plurality of memory cells stacked on a substrate, a plurality of word lines connected with the memory cell array, a plurality of pass voltage generators, and a voltage control circuit. The pass voltage generators each include a plurality of current paths and are configured to generate pass driving signals applied to unselected word lines of the plurality of word lines. The voltage control circuit is configured to control rising slopes of the pass driving signals generated from the plurality of pass voltage generators, based on adjusting the number of current paths in each pass voltage generator used to generate each driving signal.

Abstract: A method of programming a nonvolatile memory device comprises applying at least one test program pulse to selected memory cells located in a scan read area, performing a scan read operation on the selected memory cells following application of the at least one test program pulse to detect at least one one-shot upper cell, calculating an offset voltage corresponding to a scan read region at which the scan read operation is performed, setting a program start bias using the offset voltage, and executing at least one program loop using the program start bias.

Abstract: A nonvolatile memory device includes a memory cell array, a row decoder, a page buffer, and control logic. The memory cell array includes memory cells connected to word lines and bit lines, the memory cell array being configured to store data. The row decoder is configured to selectively activate a string selection line, a ground selection line, and the word lines of the memory cell array. The page buffer is configured to temporarily store external data and to apply a predetermined voltage to the bit lines according to the stored data during a program operation, and to sense data stored in selected memory cells using the bit lines during a read operation or a verification operation. The control logic is configured to control the row decoder and the page buffer. During execution of commands, when a request to suspend the execution of the commands is retrieved, chip information is backed up to a storage space separate from the control logic.

Abstract: A nonvolatile memory has a first memory block including a plurality of sub memory blocks stacked in a direction perpendicular to a substrate, and a second memory block including a plurality of sub memory blocks stacked in a direction perpendicular to the substrate, the second memory block being parallel to the first memory block. Management data unchanged after it is programmed once is stored in at least one sub memory block of the first memory block and main data is stored in sub memory blocks of the second memory block. Meta data may be stored in a sub memory block of the first memory block of in any memory block that does not contain the management data.

Abstract: A method is provided for operating a nonvolatile memory comprising memory cells stacked on a substrate. The method comprises counting a number of program loops performed in a first program operation of selected memory cells connected to a selected wordline, and controlling an increment of a program voltage between successive program loops of a second program operation of the selected memory cells according to the counted number.

Abstract: A nonvolatile memory comprises a memory block having memory cells stacked in a three dimensional structure. The nonvolatile memory device performs an erase operation to erase a selected sub block among sub blocks of the memory block, a verification operation to determine whether program states of memory cells of an unselected sub block of the memory block have changed as a consequence of the erase operation, and a reprogramming operation to reprogram at least a portion of the unselected sub block upon determining that at least one of the program states have changed as a consequence of the erase operation.

Abstract: A nonvolatile memory device comprises a first memory region and a second memory region. The nonvolatile memory device is programmed by storing program data in the first memory region, performing coarse programming and fine programming to store the program data in the second memory region, and in response to a read request, accessing the program data from the first memory region or the second memory region according to a fine program flag indicating whether the coarse programming has been completed.

Abstract: A conjugated fiber having excellent flame retardancy and color fastness and an interior fabric using the same are provided. According to the present invention, a sheath-core type conjugated fiber comprises a core component of polyphenylene sulfide resin and a sheath component of polyester-based resin. A sea-island type conjugated fiber comprises an island component of polyphenylene sulfide resin and a sea component of polyester-based resin.

Abstract: In method of programming a nonvolatile memory device including a plurality of multi-level cells that store multi-bit data according to example embodiments, a least significant bit (LSB) program operation is performed to program LSBs of the multi-bit data in the plurality of multi-level cells. A most significant bit (MSB) program operation is performed to program MSBs of the multi-bit data in the plurality of multi-level cells. To perform the MSB program, an MSB pre-program operation is performed on first multi-level cells, from among the plurality of multi-level cells, that are to be programmed to a highest target program state among a plurality of target program states, and an MSB main program operation is performed to program the plurality of multi-level cells to the plurality of target program states corresponding to the multi-bit data.

Abstract: Disclosed is an erasing method for a flash memory device that includes erasing memory cells of a selected memory block and post-programming the erased memory cells to have a threshold voltage distribution with the lowest level that is at or near 0V. The post-programming includes first post-programming the memory block in the unit of memory block and second post-programming the memory block in the unit of word line.

Abstract: A polyolefin fiber includes 0.2 to 5.0 wt % of hydrophilic additive, and 0.05 to 3.00 wt % of titanium dioxide (TiO2). The polyolefin fiber may further include 0.2 to 1.0 wt % of spin finish provided on a surface thereof. The polyolefin fiber is spun to have a circular section, a modified cross-section including an X-shaped section, a Y-shaped section, a deltaic section, an oval section, a diamond section, a bladebone-shaped section, and a combined section thereof, or a combined section of the circular section and the modified cross-section. A method of producing a polyolefin fiber includes (a) melt extruding a composition which contains 93 to 99 wt % of polyolefin resin, 0.2 to 5.0 wt % of hydrophilic additive, and 0.05 to 3.00 wt % of any one titanium dioxide (TiO2) of rutile titanium dioxide, anatase titanium dioxide, and brookite titanium dioxide at 240 to 300° C. and performing winding at a spin speed of 500 to 2,000 mpm to produce a undrawn yarn, and (b) drawing the undrawn yarn at a draw ratio of 1.

Abstract: A method for programming a flash memory device comprising programming memory cells via repetition of program loops, a first of the program loops including a program execution interval and a verify read interval, a second of the program loops including the program execution interval, the verify read interval, and a judging interval. Also disclosed is a flash memory device comprising a memory cell array having memory cells arranged in rows and columns, a read/program circuit configured to perform program and read operations to the memory cell array, and a control logic circuit configured to control the read/program circuit so as to perform a judging operation according to a program loop number.

Abstract: Disclosed is an erasing method for a flash memory device that includes erasing memory cells of a selected memory block and post-programming the erased memory cells to have a threshold voltage distribution with the lowest level that is at or near 0V. The post-programming includes first post-programming the memory block in the unit of memory block and second post-programming the memory block in the unit of word line.

Abstract: A polyolefin fiber includes 0.2 to 5.0 wt % of hydrophilic additive, and 0.05 to 3.00 wt % of titanium dioxide (TiO2). The polyolefin fiber may further include 0.2 to 1.0 wt % of spin finish provided on a surface thereof. The polyolefin fiber is spun to have a circular section, a modified cross-section including an X-shaped section, a Y-shaped section, a deltaic section, an oval section, a diamond section, a bladebone-shaped section, and a combined section thereof, or a combined section of the circular section and the modified cross-section. A method of producing a polyolefin fiber includes (a) melt extruding a composition which contains 93 to 99 wt % of polyolefin resin, 0.2 to 5.0 wt % of hydrophilic additive, and 0.05 to 3.00 wt % of any one titanium dioxide (TiO2) of rutile titanium dioxide, anatase titanium dioxide, and brookite titanium dioxide at 240 to 300° C. and performing winding at a spin speed of 500 to 2,000 mpm to produce a undrawn yarn, and (b) drawing the undrawn yarn at a draw ratio of 1.

Abstract: A method for programming a flash memory device comprising programming memory cells via repetition of program loops, a first of the program loops including a program execution interval and a verify read interval, a second of the program loops including the program execution interval, the verify read interval, and a judging interval. Also disclosed is a flash memory device comprising a memory cell array having memory cells arranged in rows and columns, a read/program circuit configured to perform program and read operations to the memory cell array, and a control logic circuit configured to control the read/program circuit so as to perform a judging operation according to a program loop number.