Patents by Inventor Dong-Hun Kwak
Dong-Hun Kwak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210249090Abstract: A nonvolatile memory device is provided. A nonvolatile memory device comprises a word line, a bit line, a memory cell array including a first memory cell at an intersection region between the word line and the bit line, a word line voltage generating circuitry configured to generate a program voltage, the program voltage to be provided to the word line, a row decoder circuitry configured to receive the program voltage from the word line voltage generating circuitry and configured to provide the program voltage to the word line, a verification circuitry configured to generate a verification signal in response to verifying a success or a failure of programming of the first memory cell, and a control circuitry configured to apply the program voltage to the first memory cell in response to the verification signal, and configured to cut off the program voltage in response to the verification signal.Type: ApplicationFiled: April 28, 2021Publication date: August 12, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Seul Bee LEE, Dong Hun KWAK, Jong-Chul PARK
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Patent number: 11074978Abstract: A memory device includes a memory cell array including a plurality of word lines, at least one select line provided above the plurality of word lines, and a channel region passing through the plurality of word lines and the at least one select line, the plurality of word lines and the channel region providing a plurality of memory cells, and a controller. The controller is to store data in a program memory cell among the plurality of memory cells by sequentially performing a first programming operation and a second programming operation, and to determine a program voltage input to a program word line connected to the program memory cell, in the first programming operation, based on information regarding the program memory cell.Type: GrantFiled: June 3, 2020Date of Patent: July 27, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Dong Hun Kwak, Sang Wan Nam, Chi Weon Yoon
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Patent number: 11024397Abstract: A nonvolatile memory device is provided. A nonvolatile memory device comprises a word line, a bit line, a memory cell array including a first memory cell at an intersection region between the word line and the bit line, a word line voltage generating circuitry configured to generate a program voltage, the program voltage to be provided to the word line, a row decoder circuitry configured to receive the program voltage from the word line voltage generating circuitry and configured to provide the program voltage to the word line, a verification circuitry configured to generate a verification signal in response to verifying a success or a failure of programming of the first memory cell, and a control circuitry configured to apply the program voltage to the first memory cell in response to the verification signal, and configured to cut off the program voltage in response to the verification signal.Type: GrantFiled: May 9, 2019Date of Patent: June 1, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Seul Bee Lee, Dong Hun Kwak, Jong-Chul Park
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Patent number: 11017838Abstract: A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.Type: GrantFiled: August 12, 2020Date of Patent: May 25, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hee-Woong Kang, Dong-Hun Kwak, Jun-Ho Seo, Hee-Won Lee
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Patent number: 10892019Abstract: A method of operating a nonvolatile memory device includes erasing data within a NAND string of memory cells within the memory device by applying a non-zero erase voltage to a source/drain terminal at a first end of the NAND string. This erase voltage is applied concurrently with establishing gate-induced drain leakage (GIDL) in a pair of selection transistors within the NAND string. This GIDL can occur by applying unequal and non-zero first and second voltages to respective first and second gate terminals of the pair of selection transistors. The selection transistors can be string selection transistors or ground selection transistors.Type: GrantFiled: February 12, 2020Date of Patent: January 12, 2021Inventors: Sang-Wan Nam, Dong-Hun Kwak, Chi-Weon Yoon
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Publication number: 20200411106Abstract: A nonvolatile memory device includes a memory cell region, a peripheral circuit region, a memory block in the memory cell region, and a control circuit in the peripheral circuit region. The memory cell region includes a first metal pad. The peripheral circuit region includes a second metal pad and is vertically connected to the memory cell region by the first metal pad and the second metal pad. The memory block includes a plurality of memory cells disposed in a vertical direction. The control circuit applies an erase voltage to an erase source terminal of the memory block, and applies a first voltage to a first selection line among a plurality of selection lines in the memory block. The first voltage is higher than the erase voltage. The first selection line is disposed closest to the erase source terminal among the plurality of selection lines and is used for selecting the memory block as an erase target block.Type: ApplicationFiled: September 9, 2020Publication date: December 31, 2020Inventors: Sang-Wan Nam, Dong-Hun Kwak, Chi-Weon Yoon
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Publication number: 20200372945Abstract: A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.Type: ApplicationFiled: August 12, 2020Publication date: November 26, 2020Inventors: Hee-Woong KANG, Dong-Hun KWAK, Jun-Ho SEO, Hee-Won LEE
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Publication number: 20200354755Abstract: The present invention relates to a novel microorganism capable of metabolizing various carbon sources at high rates. A novel microorganism according to the present invention was observed to grow at a very high rate in a minimal medium/nutrient medium, etc., compared to microorganisms such as Escherichia coli, and shows resistance at a high initial sugar/salt concentrations as well as being able to produce lycopene and 2,3-butanediol through genetic manipulation. Therefore, the novel microorganism can be used in various production fields of high value-added compounds using microorganisms.Type: ApplicationFiled: May 11, 2018Publication date: November 12, 2020Inventors: Gyoo Yeol Jung, Dong Hun Kwak, Sang Woo Seo, Hyun Gyu Lim
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Publication number: 20200350024Abstract: A method of operating a non-volatile memory device includes performing a first sensing operation on the non-volatile memory device during a first sensing time including a first section, a second section, and a third section. The performing of the first sensing operation includes applying a first voltage level, which is variable according to a first target voltage level, to a selected word line in the first section, applying a second voltage level, which is different from the first voltage level, to the selected word line in the second section, and applying the first target voltage level, which is different from the second voltage level, to the selected word line in the third section. The first voltage level becomes greater as the first target voltage level becomes greater.Type: ApplicationFiled: July 22, 2020Publication date: November 5, 2020Inventor: DONG-HUN KWAK
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Publication number: 20200294601Abstract: A memory device includes a memory cell array including a plurality of word lines, at least one select line provided above the plurality of word lines, and a channel region passing through the plurality of word lines and the at least one select line, the plurality of word lines and the channel region providing a plurality of memory cells, and a controller. The controller is to store data in a program memory cell among the plurality of memory cells by sequentially performing a first programming operation and a second programming operation, and to determine a program voltage input to a program word line connected to the program memory cell, in the first programming operation, based on information regarding the program memory cell.Type: ApplicationFiled: June 3, 2020Publication date: September 17, 2020Inventors: Dong Hun KWAK, Sang Wan NAM, Chi Weon YOON
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Patent number: 10777254Abstract: A nonvolatile memory device includes a memory cell array, a voltage generator, a page buffer circuit, a row decoder and a control circuit. The memory cell array includes a plurality of mats corresponding to different bit-lines. The voltage generator generates word-line voltages applied to the memory cell array. The page buffer circuit is coupled to the memory cell array through bit-lines. The row decoder is coupled to the memory cell array through word-lines, and the row decoder transfers the word-line voltages to the memory cell array. The control circuit controls the voltage generator, the row decoder and the page buffer circuit based on a command and an address. The control circuit selects a voltage between different voltages to apply the selected different voltages to at least one of the word-lines or at least one of the bit-lines according to a number of mats of the plurality mats, which operate simultaneously.Type: GrantFiled: March 13, 2020Date of Patent: September 15, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Hun Kwak, Hee-Woong Kang, Jun-Ho Seo, Hee-Won Lee
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Patent number: 10748621Abstract: A memory device includes a memory cell array including a plurality of word lines, at least one select line provided above the plurality of word lines, and a channel region passing through the plurality of word lines and the at least one select line, the plurality of word lines and the channel region providing a plurality of memory cells, and a controller. The controller is to store data in a program memory cell among the plurality of memory cells by sequentially performing a first programming operation and a second programming operation, and to determine a program voltage input to a program word line connected to the program memory cell, in the first programming operation, based on information regarding the program memory cell.Type: GrantFiled: August 24, 2018Date of Patent: August 18, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Dong Hun Kwak, Sang Wan Nam, Chi Weon Yoon
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Patent number: 10712955Abstract: A non-volatile memory device having a memory chip is provided. The memory chip having a memory cell array including a plurality of memory planes sharing a pad, the pad configured to communicate input and output signals. The memory chip also having a control circuit configured to monitor operations of the plurality of memory planes, and control an operation of at least one of the plurality of memory planes based on a result of the monitoring such that peak power intervals of the plurality of memory planes are at least partially distributed.Type: GrantFiled: September 28, 2018Date of Patent: July 14, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Su-chang Jeon, Sang-won Park, Dong-kyo Shim, Dong-hun Kwak
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Publication number: 20200219552Abstract: A nonvolatile memory device includes a memory cell array, a voltage generator, a page buffer circuit, a row decoder and a control circuit. The memory cell array includes a plurality of mats corresponding to different bit-lines. The voltage generator generates word-line voltages applied to the memory cell array. The page buffer circuit is coupled to the memory cell array through bit-lines. The row decoder is coupled to the memory cell array through word-lines, and the row decoder transfers the word-line voltages to the memory cell array. The control circuit controls the voltage generator, the row decoder and the page buffer circuit based on a command and an address. The control circuit selects a voltage between different voltages to apply the selected different voltages to at least one of the word-lines or at least one of the bit-lines according to a number of mats of the plurality mats, which operate simultaneously.Type: ApplicationFiled: March 13, 2020Publication date: July 9, 2020Inventors: Dong-Hun KWAK, Hee-Woong KANG, Jun-Ho SEO, Hee-Won LEE
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Patent number: 10692578Abstract: Provided is a method performed by a nonvolatile memory device, the method may include: initiating a first program operation corresponding to a first program loop among a plurality of program loops; receiving a suspend command for an urgent read operation during the first program operation; determining a recovery timing from either of a first timing contemporaneous with the receiving the suspend command, and a second timing after completion of the first program operation, based on the suspend command; and initiating a recovery at the determined recovery timing by applying a recovery voltage to a selected word line.Type: GrantFiled: April 17, 2018Date of Patent: June 23, 2020Assignee: SAMSUNG ELECTRONICS CO., LTDInventors: Su-chang Jeon, Kui-han Ko, Dong-hun Kwak, Jin-young Kim
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Publication number: 20200194086Abstract: A method of operating a non-volatile memory device includes performing a first sensing operation on the non-volatile memory device during a first sensing time including a first section, a second section, and a third section. The performing of the first sensing operation includes applying a first voltage level, which is variable according to a first target voltage level, to a selected word line in the first section, applying a second voltage level, which is different from the first voltage level, to the selected word line in the second section, and applying the first target voltage level, which is different from the second voltage level, to the selected word line in the third section. The first voltage level becomes greater as the first target voltage level becomes greater.Type: ApplicationFiled: August 21, 2019Publication date: June 18, 2020Inventor: DONG-HUN KWAK
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Publication number: 20200185038Abstract: A method of operating a nonvolatile memory device includes erasing data within a NAND string of memory cells within the memory device by applying a non-zero erase voltage to a source/drain terminal at a first end of the NAND string. This erase voltage is applied concurrently with establishing gate-induced drain leakage (GIDL) in a pair of selection transistors within the NAND string. This GIDL can occur by applying unequal and non-zero first and second voltages to respective first and second gate terminals of the pair of selection transistors. The selection transistors can be string selection transistors or ground selection transistors.Type: ApplicationFiled: February 12, 2020Publication date: June 11, 2020Inventors: Sang-Wan Nam, Dong-Hun Kwak, Chi-Weon Yoon
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Patent number: 10679702Abstract: A memory device includes a first memory area, a second memory area, a third memory area and a controller. The first memory area has a plurality of first memory cells sharing a first channel area. The second memory area has a plurality of second memory cells sharing the first channel area. The third memory area having a plurality of third memory cells sharing a second channel area, the second channel area being different from the first channel area, the first channel area and the second channel area being connected to a bit line. The controller is configured to input a voltage for the second memory cells to the second memory cells and a voltage for the third memory cells to the third memory cells, when a controlling operation is performed on the first memory cells, the voltages for the second and third memory cells having different magnitudes.Type: GrantFiled: September 10, 2018Date of Patent: June 9, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Dong Hun Kwak, Sang Wan Nam, Chi Weon Yoon
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Patent number: 10672454Abstract: A nonvolatile memory device includes a memory cell array, a voltage generator, a page buffer circuit, a row decoder and a control circuit. The memory cell array includes a plurality of mats corresponding to different bit-lines. The voltage generator generates word-line voltages applied to the memory cell array. The page buffer circuit is coupled to the memory cell array through bit-lines. The row decoder is coupled to the memory cell array through word-lines, and the row decoder transfers the word-line voltages to the memory cell array. The control circuit controls the voltage generator, the row decoder and the page buffer circuit based on a command and an address. The control circuit selects a voltage between different voltages to apply the selected different voltages to at least one of the word-lines or at least one of the bit-lines according to a number of mats of the plurality mats, which operate simultaneously.Type: GrantFiled: November 6, 2019Date of Patent: June 2, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Hun Kwak, Hee-Woong Kang, Jun-Ho Seo, Hee-Won Lee
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Publication number: 20200143897Abstract: A nonvolatile memory device is provided. A nonvolatile memory device comprises a word line, a bit line, a memory cell array including a first memory cell at an intersection region between the word line and the bit line, a word line voltage generating circuitry configured to generate a program voltage, the program voltage to be provided to the word line, a row decoder circuitry configured to receive the program voltage from the word line voltage generating circuitry and configured to provide the program voltage to the word line, a verification circuitry configured to generate a verification signal in response to verifying a success or a failure of programming of the first memory cell, and a control circuitry configured to apply the program voltage to the first memory cell in response to the verification signal, and configured to cut off the program voltage in response to the verification signal.Type: ApplicationFiled: May 9, 2019Publication date: May 7, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Seul Bee LEE, Dong Hun KWAK, Jong-Chul PARK