Abstract: An electronic device includes an internal voltage generation circuit configured to detect a voltage level of an internal voltage, that is generated by the internal voltage generation circuit. The internal voltage generating circuit is also configured to generate a drive code, which, along with a drive clock, determines the magnitude of the generated internal voltage. The drive code may be reset responsive to the internal voltage. The electronic device also includes a load circuit which is powered by the generated internal voltage.

Abstract: The method for treating wastewater includes a first flocculation-and-sedimentation process and a second flocculation-and-sedimentation process, wherein the first flocculation-and-sedimentation process include: passing wastewater through a first flocculation reaction tank; passing the first treated water through a third flocculation reaction tank; passing the third treated water through a fourth flocculation reaction tank; and passing the fourth treated water through a first sedimentation tank to generate fifth treated water and sludge, and the second flocculation-and-sedimentation process include: passing the fifth treated water through a fifth flocculation reaction tank to generate sixth treated water; passing the sixth treated water through a sixth flocculation reaction tank to generate sixth treated water; passing the sixth treated water through a seventh flocculation reaction tank to generate eighth treated water; and passing the eighth treated water through a second sedimentation tank to generate ninth t

Abstract: A semiconductor system includes a controller configured to transmit a command address and a plurality of read strobe signals, and a semiconductor device including a first rank and a second rank that are configured to receive the command address and the plurality of read strobe signals and to perform a write operation and a read operation based on the command address. In the semiconductor device, the first rank is configured to calibrate a termination resistance value of the first rank to a target resistance value when a write operation for the first rank is performed. In the semiconductor device, the first rank is configured to calibrate the termination resistance value of the first rank to a dynamic resistance value based on the plurality of read strobe signals when a write operation for the second rank is performed.

Abstract: A data output buffer includes a first driver configured to drive a data input/output (I/O) pad according to an input signal and allow data drivability to be controlled according to an impedance calibration code and a second driver configured to perform a de-emphasis operation on the data I/O pad and allow de-emphasis drivability to be controlled according to the impedance calibration code.

Abstract: A semiconductor system includes a controller, configured to: adjust a duty ratio of a data clock according to a system rate in a half rate section, generate a transmission data clock and, transmit the transmission data clock through a channel. The system also includes a semiconductor device configured to receive the transmission data clock through the channel as a reception data clock, and generate an internal data clock for a data input and output operation, based on the reception data clock.

Abstract: A semiconductor system includes a controller configured to output a command address, data, and a write clock and an inverted write clock for latching the data through a channel, configured to output the write clock and the inverted write clock having a first set level and a second set level, respectively, by incorporating information with regard to characteristics of the channel during a pre-level interval, and configured to output the write clock and the inverted write clock that periodically toggle during a toggle interval, and a semiconductor device configured to latch and store the data in synchronization with the write clock and the inverted write clock.

Abstract: Disclosed are a method and apparatus for reusing wastewater. The method for reusing wastewater disclosed herein includes: generating a mixed wastewater by mixing multiple types of wastewater (S20); performing a first purification by passing the mixed wastewater through a flocculation-sedimentation unit (S40); performing a second purification by passing an effluent of the flocculation-sedimentation unit through a membrane bioreactor (MBR) (S60); performing a third purification by passing an effluent of the MBR through a reverse-osmosis membrane unit (S80); and reusing an effluent of the reverse-osmosis membrane unit as cooling water or industrial water (S100).

Abstract: A semiconductor device includes a command pulse generation circuit configured to generate a first command pulse in synchronization with a frequency division clock and to generate a second command pulse in synchronization with an inverted frequency division clock, based on a test write command. The semiconductor device also includes an alignment data generation circuit configured to align first internal data in an in-phase manner to generate first alignment data, based on the first command pulse, and to align second internal data in an out-of-phase manner to generate second alignment data, based on the second command pulse. The semiconductor device further includes a phase detection circuit configured to determine synchronization states of a clock and the frequency division clock, based on the first alignment data and the second alignment data.

Abstract: Disclosed are a method and apparatus for reusing wastewater. The method for reusing wastewater disclosed herein includes: generating a mixed wastewater by mixing multiple types of wastewater (S20); performing a first purification by passing the mixed wastewater through a flocculation-sedimentation unit (S40); performing a second purification by passing an effluent of the flocculation-sedimentation unit through a membrane bioreactor (MBR) (S60); performing a third purification by passing an effluent of the MBR through a reverse-osmosis membrane unit (S80); and reusing an effluent of the reverse-osmosis membrane unit as cooling water or industrial water (S100).

Abstract: An amplifier circuit includes a first input unit, a second input unit, a first current supply unit, and a second current supply unit. The first input unit changes a voltage level of a first output node based on a first input signal. The second input unit changes a voltage level of a second output node based on a second input signal. The first current supply unit supplies a first current to the first output node based on a voltage level of the first output node and boosts the voltage level of the first output node for a predetermined time when the voltage level of the first output node is changed. The second current supply unit supplies a second current to the second output node based on the voltage level of the first output node.

Abstract: A semiconductor system includes a controller configured to transmit a command address and a plurality of read strobe signals, and a semiconductor device including a first rank and a second rank that are configured to receive the command address and the plurality of read strobe signals and to perform a write operation and a read operation based on the command address. In the semiconductor device, the first rank is configured to calibrate a termination resistance value of the first rank to a target resistance value when a write operation for the first rank is performed. In the semiconductor device, the first rank is configured to calibrate the termination resistance value of the first rank to a dynamic resistance value based on the plurality of read strobe signals when a write operation for the second rank is performed.

Abstract: A data output buffer includes a first driver configured to drive a data input/output (I/O) pad according to an input signal and allow data drivability to be controlled according to an impedance calibration code and a second driver configured to perform a de-emphasis operation on the data I/O pad and allow de-emphasis drivability to be controlled according to the impedance calibration code.

Abstract: A memory system includes a memory controller and a memory device. The memory controller accesses the memory device by providing a system clock signal, a data clock signal, and a chip selection signal and provides a data clock enable signal to the memory device after the access to the memory device. The memory device communicates with the memory controller based on the system clock signal, the data clock signal, and the data clock enable signal.

Abstract: A data output buffer includes a first driver configured to drive a data input/output (I/O) pad according to an input signal and allow data drivability to be controlled according to an impedance calibration code and a second driver configured to perform a de-emphasis operation on the data I/O pad and allow de-emphasis drivability to be controlled according to the impedance calibration code.

Abstract: An electrostatic precipitating apparatus for an air conditioning system is disclosed. The precipitating apparatus includes an electrostatic precipitator including a plurality of discharge electrodes to which a voltage is applied and a plurality of electrostatic precipitating electrodes each disposed between the discharge electrodes and grounded, a washing water supply spraying the washing water to the electrostatic precipitator, and a frame assembly fixed to the duct to support the electrostatic precipitator. The frame assembly is fixed to the duct to support the electrostatic precipitator, and includes a prestressing locking member fixed to inside of the duct in a state in which a pressing force is applied to the electrostatic precipitator.

Abstract: A duobinary receiver includes a signal dividing circuit configured to output a plurality of data by dividing an input signal according to a plurality of multi-phase sampling clocks signals; a level detecting circuit configured to output a plurality of state signals respectively corresponding to duobinary levels of the plurality of data; and a data converting circuit configured to decode the plurality of state signals to output a corresponding plurality of bits.

Abstract: A handover method for managing WBSS vehicle network managed by a WESS-CM includes: recognizing that a vehicle enters an overlapped area between first and second WBSSs; sending, by the first WBSS, a handover recommend request to the WESS-CM; confirming with the second WBSS, by the WESS-CM, whether handover is possible; responding to the WESS-CM, by the second WBSS, the availability of the handover after allocating communication resources; sending, by the WESS-CM, a handover recommend response to the first WBSS; transmitting, by the first WBSS, a handover request message to the vehicle; performing the handover, by the vehicle, by performing reassociation with the second WBSS; and periodically broadcasting, by the vehicle, basic safety message using a T-slot in shared control channel and a T-slot in BSM channel for the second WBSS, while the vehicle is located in the overlapped area.

Abstract: Disclosed herein is an electrostatic precipitation method using an electrostatic precipitator including a collection module having a collection electrode and a discharge electrode, a housing having an internal partition wall formed therein, an inlet-side passage switching member, and an outlet-side passage switching member. The electrostatic precipitation method includes collecting dust by applying a voltage to the discharge electrode while gas flows, closing some of the flow spaces, divided by the internal partition wall using the passage switching members, and performing dust collection for one of the opened flow spaces by applying a voltage to the discharge electrode therein, and performing washing for at least one of the closed flow spaces by supplying washing water to the collection electrode therein.

Abstract: An electrostatic precipitating apparatus for a cooling tower is provided. The precipitating apparatus include an electrostatic precipitator including a plurality of discharge electrodes to which a voltage is applied and a plurality of electrostatic precipitating electrodes each disposed between the discharge electrodes and grounded, a washing water supply spraying the washing water to the electrostatic precipitator, and a frame assembly supporting the electrostatic precipitator. The electrostatic precipitator includes a first setting beam having a plurality of lower slots into which the discharge electrodes are fixedly inserted, and the frame assembly includes a lower frame extending in a stacking direction of the discharge electrodes to support the first setting beam, via which a voltage is applied to the discharge electrode.

Abstract: Disclosed herein is a dust collecting tower apparatus that includes a housing having an inlet, into which gas is introduced, and an outlet from which the gas is discharged, and a collection module disposed in the housing and configured to collect particulates with a corona discharge. The collection module includes a plurality of discharge electrodes, to which a voltage is applied, a plurality of collection electrodes disposed between the respective discharge electrodes, where the collection electrodes is grounded, and a first setting beam having a plurality of lower slots into which the discharge electrodes are inserted. The apparatus further includes a washing water feeder configured to spray washing water to the collection module.