Abstract: A method of forming a semiconductor with n-channel and p-channel transistors with optimum gate to drain overlap capacitances for each of the different types of transistors, uses differential spacing on gate electrodes for the respective transistors. A first offset spacer is formed on the gate electrode and an n-channel extension implant is performed to create source/drain extensions for the n-channel transistors spaced an optimum distance away from the gate electrodes. Second offset spacers are formed on the first offset spacers, and a p-channel source/drain extension implant is formed to create source/drain extensions for the p-channel transistors. The increased spacing of the source/drain extension implants away from the gate electrodes in the p-channel transistors accounts for the faster diffusion of the p-type dopants in comparison to the n-type dopants.

Abstract: A MOSFET formed in semiconductor-on-insulator format. The MOSFET includes a source and a drain formed in a layer of semiconductor material, each having an extension region and a deep doped region. A body is formed between the source and the drain and includes a first damaged region adjacent the extension of the source and a second damaged region adjacent the extension of the drain. The first and second damaged regions include defects caused by amorphization of the layer of semiconductor material. A gate electrode, the source, the drain and the body are operatively arranged to form a transistor.

Abstract: A transistor on an SOI wafer has a subsurface recombination area within its body. The recombination area includes one or more doped subsurface islands, the doped islands having the same conductivity type as that of a source and a drain on opposite sides of the body, and having an opposite conductivity type from the remainder of the body. The doped subsurface island(s) may be formed by a doping implant into a surface semiconductor layer, for example through an open portion of a doping mask, the opening portion created for example by removal of a dummy gate. The doping of the islands may be performed so that the doping level of the island(s) is approximately the same as that of the body, thus enabling both Shockley-Read-Hall (SRH) and Auger recombination to take place.

Abstract: An integrated test circuit for a silicon on insulator circuit structure is formed on the same wafer as the circuit structure. The wafer includes an input circuit coupled to the silicon on insulator circuit structure which generates a drive signal for operating the silicon on insulator circuit structure and an output circuit which processes a response signal from the circuit structure to generate an output signal representing certain characteristics of the silicon on insulator circuit structure.

Abstract: A transistor device formed on a semiconductor-on-insulator (SOI) substrate with a buried oxide (BOX) layer disposed thereon and an active layer disposed on the BOX layer having active regions defined by isolation trenches. The device includes a gate defining a channel interposed between a source and a drain formed within the active region of the SOI substrate. Further, the device includes a plurality of thin silicide layers formed on the source and the drain. Additionally, at least an upper silicide layer of the plurality of thin silicide layers extends beyond a lower silicide layer. Further still, the device includes a plurality of spacers used in the formation of the device. The device further includes a second plurality of thin silicide layers formed on a polysilicon electrode of the gate.

Abstract: A semiconductor-on-insulator (SOI) device. The SOI device includes an SOI wafer including an active layer, a substrate and a buried insulation layer disposed therebetween. The active layer includes an abrupt region disposed along a lower portion of the active layer, the abrupt region having the same P or N doping type as a doping type of a body region.

Abstract: A device and method for making a semiconductor-on-insulator (SOI) structure having a leaky, thermally conductive material (LTCIM) layer disposed between a semiconductor substrate and a semiconductor layer.

Abstract: According to the invention, a method and circuit for measuring a transient of a MOFSET device under measurement of an SOI is provided. The device under measurement is connected from its drain to a measuring circuit having a trip point switching circuit. A supply voltage is applied to the drain through a capacitor connected to ground. When a high to low voltage pulse is applied to the source of the device, the threshold trip point can be determined whereby the dump charge through the transistor device can be determined.

Abstract: In one embodiment, the present invention relates to a method of forming a Silicon-on-Insulator substrate involving providing a structure comprising a bulk silicon layer, a buried insulation layer over the bulk silicon layer, a silicon device layer over the buried insulation layer, and a mask layer over the silicon device layer; etching portions of the mask layer, the silicon device layer, and the buried insulation layer thereby forming openings and exposing portions of the bulk silicon layer; depositing polysilicon in the openings; removing a portion of the polysilicon in the openings to form polysilicon sidewalls adjacent the silicon device layer and the buried insulation layer and to form gaps at least partially surrounded by the polysilicon sidewalls; depositing an insulation material in the gaps; and removing the mask layer.

Abstract: A silicon substrate comprises a silicon-on-insulator (SOI) portion which includes an insulating silicon dioxide layer beneath a device layer. SOI circuit structures, including SOI field effect transistors, are formed in the device layer. The substrate also comprises a bulk portion. Bulk semiconductor circuit structures are formed in wells in the bulk portion. The bulk circuit structures may be coupled to the SOI circuit structures.

Abstract: A transistor device formed on a semiconductor-on-insulator (SOI) substrate with a buried oxide (BOX) layer disposed thereon and an active layer disposed on the BOX layer having active regions defined by isolation trenches. The device includes a gate defining a channel interposed between a source and a drain formed within the active region of the SOI substrate. Further, the device includes a plurality of thin silicide layers formed on the source and the drain. Additionally, at least an upper silicide layer of the plurality of thin silicide layers extends beyond a lower silicide layer. Further still, the device includes a disposable spacer used in the formation of the device. The device further includes a second plurality of thin silicide layers formed on a polysilicon electrode of the gate.

Abstract: A transistor device formed on a semiconductor-on-insulator (SOI) substrate with a buried oxide (BOX) layer disposed thereon and an active layer disposed on the BOX layer having active regions defined by isolation trenches. The device includes a gate defining a channel interposed between a source and a drain formed within the active region of the SOI substrate. Further, the device includes a multi-thickness silicide layer formed on the main source and drain regions and source and drain extension regions wherein a portion of the multi-thickness silicide layer which is formed on the source and drain extension regions is thinner than a portion of the silicide layer which is formed on the main source and drain regions. The device further includes a second thin silicide layer formed on a polysilicon electrode of the gate.

Abstract: A device and method for making a semiconductor-on-insulator (SOI) structure having an insulator layer disposed between a semiconductor substrate and a semiconductor layer. An interface between the insulator layer and the semiconductor layer bleeds off extra carriers. Active regions are defined in the semiconductor layer by isolation trenches and the insulator layer.

Abstract: A device and method for making a semiconductor-on-insulator (SOI) structure having a polysilicon layer disposed between a semiconductor substrate and a semiconductor layer.

Abstract: A silicon on insulator (SOI) field effect transistor (FET) structure is formed on a conventional bulk silicon wafer. The structure includes an electrical coupling between the channel region of the FET with the bulk silicon substrate to eliminate the floating body effect caused by charge accumulation in the channel regions due to historical operation of the FET. The method of forming the structure includes isolating the FET active region from other structures in the silicon substrate by forming an insulating trench about the perimeter of the FET and forming an undercut beneath the active region to reduce or eliminate junction capacitance between the source and drain regions and the silicon substrate.

Abstract: A silicon on insulator (SOI) field effect transistor (FET) structure is formed on a conventional bulk silicon wafer. The structure includes an electrical coupling between the channel region of the FET with the bulk silicon substrate to eliminate the floating body effect caused by charge accumulation in the channel regions due to historical operation of the FET. The method of forming the structure includes isolating the FET active region from other structures in the silicon substrate by forming an insulating trench about the perimeter of the FET and forming an undercut beneath the active region to reduce or eliminate junction capacitance between the source and drain regions and the silicon substrate.

Abstract: In one embodiment, the present invention relates to a method of forming a Silicon-on-Insulator substrate involving providing a structure comprising a bulk silicon layer, a buried insulation layer over the bulk silicon layer, a silicon device layer over the buried insulation layer, and a mask layer over the silicon device layer; etching portions of the mask layer, the silicon device layer, and the buried insulation layer thereby forming openings and exposing portions of the bulk silicon layer; depositing polysilicon in the openings; removing a portion of the polysilicon in the openings to form polysilicon sidewalls adjacent the silicon device layer and the buried insulation layer and to form gaps at least partially surrounded by the polysilicon sidewalls; depositing an insulation material in the gaps; and removing the mask layer.

Abstract: A semiconductor device with shallow junctions is obtained by forming shallow source/drain extensions followed by forming a film over the gate electrode and the semiconductor substrate. The film is formed having a targeted thicknesses to facilitate gate electrode doping and source/drain formation. Ion implantation is then conducted to fully dope the gate electrode and form moderately or heavily doped source/drain implants, thereby reducing gate depletion.

Abstract: The present invention is directed to a metal oxide semiconductor transistor having a fully overlapped lightly doped drain (LDD) structure which offers the advantages of conventional fully overlapped LDD transistors but which significantly reduces the drain-to-gate overlap capacitance associate therewith. To achieve fully overlapped LDD construction and reduced drain-to-gate overlap capacitance, the metal oxide semiconductor transistor of the present invention employs a gate electrode comprising a main gate region formed from heavily doped polysilicon and depleted sidewall polysilicon spacers formed from undoped or depleted polysilicon. In the MOS transistor of the present invention, the lightly doped regions are fully over-lapped by the combination of the depleted sidewall polysilicon spacers and the main gate region.

Abstract: A semiconductor device is provided with a gate electrode having a substantially rectangular profile by forming a dielectric film prior to depositing the gate electrode layer. The dielectric film is patterned and etched to form regions having a rectangular profile separated by open regions. A gate electrode layer is then deposited followed by planarization to form gate electrodes having a substantially rectangular profile.