Abstract: Disclosed herein are an inverter and an antenna circuit. The inverter that receives control signals, inverts the control signals including a first control signal, a second control signal, and a third control signal, and outputs the inverted control signals, includes: a first MOS transistor having a gate to which a first control signal is applied and a source that is grounded; a second MOS transistor having a gate to which a third control signal is applied and a source to which a second control signal is applied; and a third MOS transistor having a gate to which a second control signal is applied and a source to which a third control signal is applied, wherein drains of the first MOS transistor, the second MOS transistor, and the third MOS transistor are connected to an output terminal.

Abstract: A card-type information recording medium having an embedded antenna for NFC communication is provided. The card-type information recording medium includes: a PCB that has a loop antenna pattern and a routing pattern formed on the top surface and the bottom surface thereof through the use of an etching process; an NFC communication unit and a USIM card unit that are horizontally mounted on the top of the PCB; and a molding material that is formed on the top of the PCB to cover the NFC communication unit and the USIM card unit. Accordingly, it is possible to perform functions of NFC and RFID read/tag by only mounting a USIM device thereon without adding any module or any constituent having an antenna function to a mobile terminal.

Abstract: A radio frequency (RF) switch circuit is disclosed to restrict an input signal input to the RF switch from being transferred to a switch controller when a floating resistor is connected to an NMOS FET and a PMOS FET of the RF switch and the switch controller formed through a standard CMOS (Complementary Metal Oxide Semiconductor) process.

Abstract: A radio frequency (RF) switch circuit in which an RF switch and a switch controller are formed on a single CMOS substrate and floating resistors are connected to a deep N type well substrate, an N type well substrate, and a P type well substrate to thereby increase linearity with respect to input power.

Abstract: A small-sized on-chip complementary metal-oxide semiconductor (CMOS) Power Amplifier having improved efficiency is provided herein. The on-chip CMOS power amplifier is capable of improving efficiency and maximizing output thereof by enhancing a K factor, which may cause a problem in a power amplifier having a distributed active transformer structure. The on-chip CMOS power amplifier having an improved efficiency and being fabricated in a small size, the on-chip CMOS power amplifier includes a primary winding located at a first layer, secondary windings located at a second layer, which is an upper part of the first layer, the secondary windings being located corresponding to a position of the primary winding, and a cross section for coupling the second windings with each other.

Abstract: A high efficiency power amplifier with a precise duty cycle is provided for use in a driver or pre-power amplifier of a Radio Frequency (RF) system. The high efficiency power amplifier with an inverter configured by one pair of Metal Oxide Semiconductor (MOS) transistors includes a feedback path for adjusting an input voltage in response to an output voltage between input and output terminals of the inverter and correcting an operation time point of the MOS transistors configuring the inverter. The high efficiency power amplifier can be used for a high efficiency driver to automatically correct duty cycle distortion. When the high efficiency power amplifier is placed in a front stage of various RF power amplifiers, it can be used for a pre-amplifier capable of increasing the efficiency of the RF power amplifier.

Abstract: A small-sized on-chip complementary metal-oxide semiconductor (CMOS) Power Amplifier having improved efficiency is provided herein. The on-chip CMOS power amplifier is capable of improving efficiency and maximizing output thereof by enhancing a K factor, which may cause a problem in a power amplifier having a distributed active transformer structure. The on-chip CMOS power amplifier having an improved efficiency and being fabricated in a small size, the on-chip CMOS power amplifier includes a primary winding located at a first layer, secondary windings located at a second layer, which is an upper part of the first layer, the secondary windings being located corresponding to a position of the primary winding, and a cross section for coupling the second windings with each other.