Abstract: A non-volatile memory device includes a plurality of word lines, a plurality of bit lines, and an array of variable resistance memory cells each electrically connected between a respective word line and a respective bit line. Each of the memory cells includes first and second resistance variable patterns electrically connected in series between first and second electrodes. A material composition of the first resistance variable pattern is different than a material composition of the second resistance variable pattern. Multi-bit data states of each memory cell are defined by a contiguous increase in size of a programmable high-resistance volume within the first and second resistance variable patterns.

Abstract: A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.

Abstract: A method of forming a memory device includes forming a first interlayer insulating layer on a semiconductor substrate, forming a first electrode in the first interlayer insulating layer, the first electrode having a top surface of a rectangular shape extending in a first direction, and forming a variable resistance pattern on the first electrode, the variable resistance pattern having a bottom surface of a rectangular shape extending in a second direction crossing the first direction, the bottom surface of the variable resistance pattern contacting the first electrode, wherein the area of contact between the lower electrode and the variable resistance pattern is substantially equal to a multiplication of a minor axis length of a top surface of the first electrode and a minor axis length of a bottom surface of the variable resistance pattern.

Abstract: A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.

Abstract: A nonvolatile memory device and a method of fabricating the same are provided. The nonvolatile memory device includes a conductive pillar that extends from a substrate in a first direction, a variable resistor that surrounds the conductive pillar, a switching material layer that surrounds the variable resistor, a first conductive layer that extends in a second direction, and a first electrode that extends in a third direction and contacts the first conductive layer and the switching material layer. Not one of the first, second, and third directions is parallel to another one of the first, second, and third directions.

Abstract: In a method of forming a pattern, a first mask layer and a first sacrificial layer may be sequentially formed on an object layer. The first sacrificial layer may be partially etched to form a first sacrificial layer pattern. A second sacrificial layer pattern may be formed on the first mask layer. The second sacrificial layer pattern may enclose a sidewall of the first sacrificial layer pattern. The first sacrificial layer pattern may then be removed. The first mask layer may be partially etched using the second sacrificial layer pattern as an etching mask to form a first mask layer pattern. The object layer may be partially etched using the first mask layer pattern as an etching mask.

Abstract: A phase change memory device includes an impurity region on a substrate, the impurity region being in an active region, a metal silicide pattern at least partially buried in the impurity region, a diode on the impurity region, a lower electrode on the diode, a phase change layer pattern on the lower electrode, and an upper electrode on the phase change layer pattern.

Abstract: A method of forming a memory device includes forming a first interlayer insulating layer on a semiconductor substrate, forming a first electrode in the first interlayer insulating layer, the first electrode having a top surface of a rectangular shape extending in a first direction, and forming a variable resistance pattern on the first electrode, the variable resistance pattern having a bottom surface of a rectangular shape extending in a second direction crossing the first direction, the bottom surface of the variable resistance pattern contacting the first electrode, wherein the area of contact between the lower electrode and the variable resistance pattern is substantially equal to a multiplication of a minor axis length of a top surface of the first electrode and a minor axis length of a bottom surface of the variable resistance pattern.

Abstract: In a method of forming a pattern, a plurality of first line patterns and first spacers filling spaces between the adjacent first line patterns are formed on an object layer. The first line patterns and the first spacers extend in a first direction. A plurality of second line patterns are formed on the first line patterns and the first spacers. The second line patterns extend in a second direction substantially perpendicular to the first direction. The first spacers are partially removed by a wet etching process. The object layer is etched using the first and second line patterns as an etching mask.

Abstract: A method of fabricating an integrated circuit device includes forming first and second patterns extending in first and second directions, respectively, on a target layer. The first patterns comprise a metal oxide and/or metal silicate material having an etch selectivity with respect to that of the target layer. The second patterns comprise a material having an etch selectivity with respect to those of the first patterns and the target layer. The target layer is selectively etched using the first patterns and the second patterns as an etch mask to define holes respectively extending through the target layer to expose a layer therebelow. At least one of the first and second patterns is formed using respective mask patterns formed by a photolithographic process, and the at least one of the first and second patterns have a finer pitch than that of the respective mask patterns.

Abstract: A method of manufacturing the semiconductor device includes sequentially forming first to third mold layer patterns on a substrate and spaced apart from each other , forming a first semiconductor pattern between the first mold layer pattern and the second mold layer pattern, and a second semiconductor pattern between the second mold layer pattern and the third mold layer pattern, forming a first trench between the first mold layer pattern and the third mold layer pattern by removing a portion of the second mold layer pattern and portions of the first and second semiconductor patterns, depositing a material for a lower electrode conformally along side and bottom surfaces of the first trench, and forming first and second lower electrodes separated from each other on the first and second semiconductor patterns, respectively, by removing a portion of the material for a lower electrode positioned on the second mold layer pattern.

Abstract: A method of forming a memory device includes forming a first interlayer insulating layer on a semiconductor substrate, forming a first electrode in the first interlayer insulating layer, the first electrode having a top surface of a rectangular shape extending in a first direction, and forming a variable resistance pattern on the first electrode, the variable resistance pattern having a bottom surface of a rectangular shape extending in a second direction crossing the first direction, the bottom surface of the variable resistance pattern contacting the first electrode, wherein the area of contact between the lower electrode and the variable resistance pattern is substantially equal to a multiplication of a minor axis length of a top surface of the first electrode and a minor axis length of a bottom surface of the variable resistance pattern.

Abstract: A phase change material layer includes a Ge-M-Te (GMT) ternary phase change material, where Ge is germanium, M is a heavy metal, and Te is tellurium. The GMT ternary phase change material may also include a dopant.

Abstract: Provided is a non-volatile memory device including a bottom electrode disposed on a substrate and having a lower part and an upper part. A conductive spacer is disposed on a sidewall of the lower part of the bottom electrode. A nitride spacer is disposed on a top surface of the conductive spacer and a sidewall of the upper part of the bottom electrode. A resistance changeable element is disposed on the upper part of the bottom electrode and the nitride spacer. The upper part of the bottom electrode contains nitrogen (N).

Abstract: Provided are methods of forming a phase change memory device. A semiconductor device having a lower electrode and an interlayer insulating layer may be prepared. The lower electrode may be surrounded by the interlayer insulating layer. Source gases, a reaction gas and a purge gas may be injected into a process chamber of a semiconductor fabrication device to form a phase change material layer on a semiconductor substrate. The source gases may be simultaneously injected into the process chamber. The phase change material layer may be in contact with the lower electrode through the interlayer insulating layer. The phase change material layer may be etched to form a phase change memory cell in the interlayer insulating layer. An upper electrode may be formed on the phase change memory cell.

Abstract: A semiconductor device includes a switching device disposed on a substrate. A buffer electrode pattern is disposed on the switching device. The buffer electrode pattern includes a first region having a first vertical thickness, and a second region having a second vertical thickness smaller than the first vertical thickness. A lower electrode pattern is disposed on the first region of the buffer electrode pattern. A trim insulating pattern is disposed on the second region of the buffer electrode pattern. A variable resistive pattern is disposed on the lower electrode pattern.

Abstract: A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.

Abstract: A nonvolatile memory device and a method of fabricating the same are provided. The nonvolatile memory device includes a conductive pillar that extends from a substrate in a first direction, a variable resistor that surrounds the conductive pillar, a switching material layer that surrounds the variable resistor, a first conductive layer that extends in a second direction, and a first electrode that extends in a third direction and contacts the first conductive layer and the switching material layer. Not one of the first, second, and third directions is parallel to another one of the first, second, and third directions.

Abstract: Apparatus for fabricating a phase-change material layer include a process chamber. A first source supplier including a liquid delivery system (LDS) structure is coupled between a tellurium (Te) source container and the process chamber. A second source supplier including a bubbler method structure is coupled between at least one metal organic (MO) source container and the process chamber. Methods are also provided.

Abstract: Provided is a non-volatile memory device including a bottom electrode disposed on a substrate and having a lower part and an upper part. A conductive spacer is disposed on a sidewall of the lower part of the bottom electrode. A nitride spacer is disposed on a top surface of the conductive spacer and a sidewall of the upper part of the bottom electrode. A resistance changeable element is disposed on the upper part of the bottom electrode and the nitride spacer. The upper part of the bottom electrode contains nitrogen (N).