Patents by Inventor Dong-Ju Jeon

Dong-Ju Jeon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240097466
    Abstract: Disclosed is a high voltage output device having a serial-parallel stack structure of capacitors. The high voltage output device includes a substrate includes a capacitor element and a pillar structure provided on an upper surface of the substrate. The substrate includes a first electrode and a second electrode, which have different potentials from each other. The capacitor element is connected to at least one of the first electrode and the second electrode.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 21, 2024
    Applicant: JEISYS MEDICAL INC.
    Inventors: Seung Wook LEE, Seung In KANG, Yeong Gi JEON, Si Youn KIM, Kyu Young SEO, Min Young KIM, Won Ju YI, Dong Hwan KANG
  • Patent number: 10858379
    Abstract: A novel metal precursor having improved thermal stability and volatility is provided. Also provided herein are: a method for readily manufacturing a good quality metal oxide thin film at an excellent growth rate at low temperature by using the metal precursor; and a thin film manufactured by using the same.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: December 8, 2020
    Assignee: KOREA RESEARCH INSTITUTE OF CHEMICAL TECHNOLOGY
    Inventors: Bo Keun Park, Taek-Mo Chung, Dong Ju Jeon, Jeong Hwan Han, Ji Hyeun Nam, Chang Gyoun Kim, Eun Ae Jung
  • Publication number: 20180334471
    Abstract: The present invention relates to a novel metal precursor having improved thermal stability and volatility and can provide: a method for readily manufacturing a good quality metal oxide thin film at an excellent growth rate at low temperature by using the metal precursor; and a thin film manufactured by using the same.
    Type: Application
    Filed: October 11, 2016
    Publication date: November 22, 2018
    Inventors: Bo Keun PARK, Taek-Mo CHUNG, Dong Ju JEON, Jeong Hwan HAN, Ji Hyeun NAM, Chang Gyoun KIM, Eun Ae JUNG
  • Patent number: 10134664
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a dielectric core having an embedded pad; a top solder resist layer on the dielectric core, a pad top surface of the embedded pad below the top solder resist layer; a device interconnect attached to the embedded pad; and an integrated circuit device having an interconnect pillar, the interconnect pillar attached to the device interconnect for mounting the integrated circuit device to the dielectric core.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: November 20, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: MinKyung Kang, YoungDal Roh, Dong Ju Jeon, KyoungHee Park
  • Publication number: 20180282866
    Abstract: The present invention relates to a ruthenium precursor represented by Chemical Formula 1, and the ruthenium precursor has the advantages of having improved thermal stability and volatility and not having to use oxygen when depositing a thin film, and thus is capable of forming a high-quality ruthenium thin film.
    Type: Application
    Filed: May 2, 2014
    Publication date: October 4, 2018
    Inventors: Bo-Keun PARK, Taek-Mo CHUNG, Chang-Gyoun KIM, Dong-Ju JEON, Eun-Ae JUNG
  • Patent number: 9790238
    Abstract: Disclosed herein is a novel strontium precursor containing a beta-diketonate compound. Being superior in thermal stability and volatility, the strontium precursor can form a quality strontium thin film.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: October 17, 2017
    Assignee: KOREA RESEARCH INSTITUTE OF CHEMICAL TECHNOLOGY
    Inventors: Bo-Keum Park, Taek-Mo Chung, Chang-Gyoun Kim, Sheby Mary George, Young-Kuk Lee, Jong-Sun Lim, Seog-Jong Jeong, Dong-Ju Jeon, Ki-Seok An, Sun-Sook Lee
  • Patent number: 9768102
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a one-layer substrate with a symmetrical structure, the one-layer substrate having a redistribution pad and an insulation, the redistribution pad only at an insulation top side of the insulation; mounting an integrated circuit over the one-layer substrate; and forming an encapsulation over the integrated circuit.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: September 19, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Dong Ju Jeon, Koo Hong Lee, Sung Soo Kim
  • Patent number: 9743508
    Abstract: An electroless surface treatment plated layer of a printed circuit board, a method for preparing the same, and printed circuit board including the same. The electroless surface treatment plated layer includes: electroless nickel (Ni) plated coating/palladium (Pd) plated coating/gold (Au) plated coating, wherein the electroless nickel, palladium, and gold plated coatings have thicknesses of 0.02 to 1 ?m, 0.01 to 0.3 ?m, and 0.01 to 0.5 ?m, respectively. In the electroless surface treatment plated layer of the printed circuit board, a thickness of the nickel plated coating is specially minimized to 0.02 to 1 ?m, thereby making it possible to form an optimized electroless Ni/Pd/Au surface treatment plated layer.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: August 22, 2017
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Dong Jun Lee, Dong Ju Jeon, Jung Youn Pang, Seong Min Cho, Chi Seong Kim
  • Publication number: 20170162495
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a dielectric core having an embedded pad; a top solder resist layer on the dielectric core, a pad top surface of the embedded pad below the top solder resist layer; a device interconnect attached to the embedded pad; and an integrated circuit device having an interconnect pillar, the interconnect pillar attached to the device interconnect for mounting the integrated circuit device to the dielectric core.
    Type: Application
    Filed: February 15, 2017
    Publication date: June 8, 2017
    Inventors: MinKyung Kang, YoungDal Roh, Dong Ju Jeon, KyoungHee Park
  • Patent number: 9607938
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a dielectric core having an embedded pad; a top solder resist layer on the dielectric core, a pad top surface of the embedded pad below the top solder resist layer; a device interconnect attached to the embedded pad; and an integrated circuit device having an interconnect pillar, the interconnect pillar attached to the device interconnect for mounting the integrated circuit device to the dielectric core.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: March 28, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: MinKyung Kang, YoungDal Roh, Dong Ju Jeon, KyoungHee Park
  • Patent number: 9573907
    Abstract: The present invention relates to novel 2,4-pyrimidine derivatives and a use thereof, and more particularly, to pyrimidine derivatives which are effective for systemic lupus erythematosus, a composition for preventing and treating systemic lupus erythematosus comprising the same as an active ingredient and a method for screening the same. The present inventors found novel materials inhibiting surface translocation of gp96 by mimicking a function of AIMP1 which is a molecular anchor for an intracellular residence of gp96, and identified in vitro and in vivo activity of the materials for preventing and treating SLE by alleviating SLE plasma in autoimmune diseases. Therefore, the present invention provides a novel method for screening a therapeutic agent for SLE, and preventing or treating SLE using the mechanism.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: February 21, 2017
    Assignees: SNU R&DB FOUNDATION, KOREA RESEARCH INSTITUTE OF CHEMICAL TECHNOLOGY
    Inventors: Sunghoon Kim, Jung Min Han, Hyeong Rae Kim, Dong Ju Jeon, Jong Hwan Song, Kyung Eun Park
  • Publication number: 20150382452
    Abstract: An electroless surface treatment plated layer of a printed circuit board, a method for preparing the same, and printed circuit board including the same. The electroless surface treatment plated layer includes: electroless nickel (Ni) plated coating/palladium (Pd) plated coating/gold (Au) plated coating, wherein the electroless nickel, palladium, and gold plated coatings have thicknesses of 0.02 to 1 ?m, 0.01 to 0.3 ?m, and 0.01 to 0.5 ?m, respectively. In the electroless surface treatment plated layer of the printed circuit board, a thickness of the nickel plated coating is specially minimized to 0.02 to 1 ?m, thereby making it possible to form an optimized electroless Ni/Pd/Au surface treatment plated layer.
    Type: Application
    Filed: September 8, 2015
    Publication date: December 31, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Dong Jun LEE, Dong Ju JEON, Jung Youn PANG, Seong Min CHO, Chi Seong KIM
  • Patent number: 9210816
    Abstract: A method of manufacture of a support system includes: forming a carrier having a detachable core and a carrier foil directly on the detachable core; forming a mask directly on the carrier foil, the mask having a mask hole through the mask; forming a bottom conductive layer within the mask hole and directly on the carrier foil; forming an interior insulation layer directly on the bottom conductive layer and the mask after the bottom conductive layer is formed within the mask hole; partially removing the interior insulation layer leaving an insulation hole through the interior insulation layer; forming a conductive connector completely within the insulation hole; and forming a bottom exterior insulation layer over the bottom conductive layer and the mask.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: December 8, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: YoungDal Roh, KyoungHee Park, Dong Ju Jeon, HyungSang Park
  • Patent number: 9171795
    Abstract: An integrated circuit packaging system, and a method of manufacture of an integrated circuit packaging system thereof, including: an embedding material on a component; a mask layer on the embedding material; a buried pattern in the mask layer, the outer surface of the buried pattern coplanar with the outer surface of the mask layer, the buried pattern electrically connected to the component; a patterned dielectric on a portion of the buried pattern; and an integrated circuit die on the buried pattern.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: October 27, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Dong Ju Jeon, KyoungHee Park, YoungDal Roh, JinHee Jung
  • Patent number: 9150002
    Abstract: An electroless surface treatment plated layer of a printed circuit board, a method for preparing the same, and printed circuit board including the same. The electroless surface treatment plated layer includes: electroless nickel (Ni) plated coating/palladium (Pd) plated coating/gold (Au) plated coating, wherein the electroless nickel, palladium, and gold plated coatings have thicknesses of 0.02 to 1 ?m, 0.01 to 0.3 ?m, and 0.01 to 0.5 ?m, respectively. In the electroless surface treatment plated layer of the printed circuit board, a thickness of the nickel plated coating is specially minimized to 0.02 to 1 ?m, thereby making it possible to form an optimized electroless Ni/Pd/Au surface treatment plated layer.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: October 6, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Dong Jun Lee, Dong Ju Jeon, Jung Youn Pang, Seong Min Cho, Chi Seong Kim
  • Publication number: 20150175629
    Abstract: Disclosed herein is a novel strontium precursor containing a beta-diketonate compound. Being superior in thermal stability and volatility, the strontium precursor can form a quality strontium thin film.
    Type: Application
    Filed: May 3, 2013
    Publication date: June 25, 2015
    Inventors: Bo-Keun Park, Taek-Mo Chung, Chang-Gyoun Kim, Sheby Mary George, Young-Kuk Lee, Jong-Sun Lim, Seog-Jong Jeong, Dong-Ju Jeon, Ki-Seok An, Sun-Sook Lee
  • Publication number: 20150171002
    Abstract: An integrated circuit packaging system, and a method of manufacture of an integrated circuit packaging system thereof, including: an embedding material on a component; a mask layer on the embedding material; a buried pattern in the mask layer, the outer surface of the buried pattern coplanar with the outer surface of the mask layer, the buried pattern electrically connected to the component; a patterned dielectric on a portion of the buried pattern; and an integrated circuit die on the buried pattern.
    Type: Application
    Filed: December 1, 2014
    Publication date: June 18, 2015
    Inventors: Dong Ju Jeon, KyoungHee Park, YoungDal Roh, JinHee Jung
  • Publication number: 20150001705
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a dielectric core having an embedded pad; a top solder resist layer on the dielectric core, a pad top surface of the embedded pad below the top solder resist layer; a device interconnect attached to the embedded pad; and an integrated circuit device having an interconnect pillar, the interconnect pillar attached to the device interconnect for mounting the integrated circuit device to the dielectric core.
    Type: Application
    Filed: June 27, 2013
    Publication date: January 1, 2015
    Inventors: MinKyung Kang, YoungDal Roh, Dong Ju Jeon, KyoungHee Park
  • Publication number: 20130249078
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a one-layer substrate with a symmetrical structure, the one-layer substrate having a redistribution pad and an insulation, the redistribution pad only at an insulation top side of the insulation; mounting an integrated circuit over the one-layer substrate; and forming an encapsulation over the integrated circuit.
    Type: Application
    Filed: March 21, 2012
    Publication date: September 26, 2013
    Inventors: Dong Ju Jeon, Koo Hong Lee, Sung Soo Kim
  • Publication number: 20130000960
    Abstract: Disclosed herein are a printed circuit board and a method for manufacturing the same. The printed circuit board includes: a copper pad surface roughness-treated to have a surface roughness of 0.1 to 1.0 ?m pitch period; and an electroless surface treatment plating layer formed on the copper pad. According to the present invention, when the copper pad has a surface roughness of a predetermined pitch period, the electroless surface treatment plating layer formed on the copper pad also has a surface roughness of the predetermined pitch period, thereby having an effect of widening a surface area and improving workability at the time of a wire bonding process for connection with an external device.
    Type: Application
    Filed: May 15, 2012
    Publication date: January 3, 2013
    Inventors: Dong Jun LEE, Dong Ju Jeon, Jung Youn Pang, Seong Min Cho, Chi Seong Kim