Abstract: A method is for programming a memory block of a non-volatile memory device. The non-volatile memory device is operatively connected to a memory controller, and the memory block defined by a plurality of word lines located between a string select line and a common source line corresponding to the string select line. The method includes programming a first sub-block of the memory block, determining in the non-volatile memory device when a reference word line is programmed during programming of the first sub-block, and partial erasing a second sub-block of the memory block upon determining that the reference word line is programmed during programming of the first sub-block.

Abstract: A flash memory system includes a multi-bit flash memory device having a memory cell array including memory cells arranged in rows and columns; a read circuit configured to read data from the memory cell array; and control logic configured to control the read circuit so as to successively read data from a selected memory cell and adjacent memory cells to the selected memory cell in response to a request for a read operation with respect to MSB data stored in the selected memory cell. A compare circuit is configured to compare data read from the adjacent memory cells to the selected memory cell provided from the multi-bit flash memory device and to correct data read from the selected memory cells based upon the comparison result.

Abstract: A flash memory device and a reading method are provided where memory cells are divided into at least two groups. Memory cells are selected according to a threshold voltage distribution. Data stored in the selected memory cells are detected and the data is latched corresponding to one of the at least two groups according to a first read operation. A second read operation detects and latches data of the memory cells corresponding to another one of the at least two groups. The data is processed through a soft decision algorithm during the second read operation.

Abstract: A nonvolatile memory device is programmed by decoding a received address, determining whether the received address is a first type of page address or a second type of page address, adjusting a maximum verify time of a program loop used to verify a program state of page data according to the determined type of page address, and performing a verify operation during the adjusted maximum verify time.

Abstract: A flash memory device and a reading method are provided where memory cells are divided into at least two groups. Memory cells are selected according to a threshold voltage distribution. Data stored in the selected memory cells are detected and the data is latched corresponding to one of the at least two groups according to a first read operation. A second read operation detects and latches data of the memory cells corresponding to another one of the at least two groups. The data is processed through a soft decision algorithm during the second read operation.

Abstract: An Error Control Code (ECC) apparatus applied to a memory of a Multi-Level Cell (MLC) method may include: a bypass control signal generator generating a bypass control signal; and an ECC performing unit that may include at least two ECC decoding blocks, determining whether to bypass a portion of the at least two ECC decoding blocks based on the bypass control signal, and/or performing an ECC decoding. In addition or in the alternative, the ECC performing unit may include at least two ECC encoding blocks, determining whether to bypass a portion of the at least two ECC encoding blocks based on the bypass control signal, and/or performing an ECC encoding. An ECC method applied to a memory of a MLC method and a computer-readable recording medium storing a program for implementing an EEC method applied to a memory of a MLC method are also disclose.

Abstract: In one embodiment, the non-volatile memory device includes a plurality of normal memory cells, and at least one flag memory cell associated with one of the plurality of normal memory cells. A normal page buffer is configured to store data read from one of the plurality of normal memory cells. The normal page buffer includes a main latch storing the read data. A control circuit is configured to selectively change data stored in the main latch during a read operation based on a state of the flag memory cell.

Abstract: A flash memory device includes a cell array and a read voltage adjuster. The cell array includes a first field having first memory cells and a second field having second memory cells. The read voltage adjuster determines a read voltage for reading first data from the first memory cells of the first field with reference to second data read from the memory cells of the second field.

Abstract: An Error Control Code (ECC) apparatus may include a control signal generator that generates an ECC control signal based on channel information. The ECC apparatus also may include: a plurality of ECC encoding controllers that output data respectively inputted via storage elements corresponding to the ECC control signal; and/or an encoding unit that encodes, using a plurality of data outputted from the plurality of ECC encoding controllers, encoding input data into a number of subdata corresponding to the ECC control signal. In addition or in the alternative, the ECC apparatus may include: a plurality of ECC decoding controllers that output data respectively inputted via the storage elements corresponding to the ECC control signal; and/or a decoding unit that decodes, using a plurality of data outputted from the plurality of ECC decoding controllers, a number of decoding input data corresponding to the ECC control signal into one piece of output data.

Abstract: A multi-level cell (MLC) memory device may include: a MLC memory cell; an outer encoder that encodes data using a first encoding scheme to generate an outer encoded bit stream; and a trellis coded modulation (TCM) modulator that applies a program pulse to the MLC memory cell to write the data in the MLC memory cell. The program pulse may be generated by TCM modulating the outer encoded bit stream. A method of storing data in a MLC memory device, reading data from the MLC memory device, or storing data in and reading data from the MLC memory device may include: encoding data using a first encoding scheme to generate an outer encoded bit stream; and applying a program pulse to a MLC memory cell of the MLC memory device to write the data in the MLC memory cell. The program pulse may be generated by TCM modulating the outer encoded bit stream.

Abstract: A Multi-Level Cell (MLC) memory device and method thereof are provided. The example MLC memory device may be configured to perform data operations, and may include an MLC memory cell, a first coding device performing a first coding function, the first coding function being one of an encoding function and a decoding function, a second coding device performing a second coding function, the second coding function being one of an encoding function and a decoding function and a signal module configured to perform at least one of instructing the MLC memory cell to store data output by the second coding device if the first and second coding functions are encoding functions, and generating a demapped bit stream based on data retrieved from the MLC memory cell if the first and second coding functions are decoding functions.

Abstract: A Multi-Level Cell (MLC) memory device and method thereof are provided. The example MLC memory device may be configured to perform data operations, and may include an MLC memory cell, a first coding device performing a first coding function, the first coding function being one of an encoding function and a decoding function, a second coding device performing a second coding function, the second coding function being one of an encoding function and a decoding function and a signal module configured to perform at least one of instructing the MLC memory cell to store data output by the second coding device if the first and second coding functions are encoding functions, and generating a demapped bit stream based on data retrieved from the MLC memory cell if the first and second coding functions are decoding functions.

Abstract: In one aspect, a non-volatile memory system includes a plurality of memory cell arrays having different read stand-by times. For example, the non-volatile memory system may include a single-level cell (SLC) array composed of a plurality of SLCs, and a multi-level cell (MLC) array composed of a plurality of MLCs. In this case, the SLC array and the MLC array receive a read instruction at the same time and prepare to read data at the same time. However, the SLC array begins to read the data prior to the MLC array, and the MLC array begins to read the data once the SLC array has completely read the data.

Abstract: Provided is a read operation for a N-bit data non-volatile memory system. The method includes determining in relation to data states of adjacent memory cells associated with a selected memory cell in the plurality of memory cells whether read data obtained from the selected memory cell requires compensation, and if the read data requires compensation, replacing the read data with compensated read data.

Abstract: A method of programming a non-volatile memory including N-bit multi-level cell (MLC) memory includes executing an incremental step pulse programming (ISPP) operation on the MLC memory cells, where the ISPP operation includes a programming sequence of first through Nth page programming operations, where N is an integer of 2 or more.

Abstract: A method of programming a non-volatile memory including N-bit multi-level cell (MLC) memory cells includes executing first through (N?1)th page programming operations, using an incremental step pulse programming (ISPP) method, to program first through (N?1)th data pages in the MLC memory cells, where each of the first through (N?1)th page programming operations includes an erase programming of erase cells among the MLC memory cells. The method further includes executing an Nth page programming operation, using the ISPP method, to program an Nth data page in the MLC memory cells.

Abstract: The flash memory device of the present invention is configured to program a plurality of bits per unit cell, wherein a program condition of a selected bit is set according to whether a program for the most previous bit to the selected bit for programming is skipped or not skipped. As a result, an accurate programming and reading operation is possible even in case a program for a middle bit is skipped.

Abstract: A memory cell programming method and related semiconductor memory device are disclosed. The method involves receiving and latching first through nth bits of write data in a corresponding plurality of first through nth latches, and programming a kth bit of write data in the memory cell, where k ranges from 2 to n, in relation to first through k?1th bits of write data previously stored in the memory cell.

Abstract: A method and apparatus for controlling a reading level of a memory cell are provided. The method of controlling a reading level of a memory cell may include: receiving metric values calculated based on given voltage levels and reference levels; generating summed values for each of the reference levels by summing metric values corresponding to levels of a received signal from among the received metric values; selecting the reference level having the greatest value of the generated summed values from the reference levels; and controlling the reading level of the memory cell based on the selected reference level.

Abstract: A flash memory system includes a multi-bit flash memory device having a memory cell array including memory cells arranged in rows and columns; a read circuit configured to read data from the memory cell array; and control logic configured to control the read circuit so as to successively read data from a selected memory cell and adjacent memory cells to the selected memory cell in response to a request for a read operation with respect to MSB data stored in the selected memory cell. A compare circuit is configured to compare data read from the adjacent memory cells to the selected memory cell provided from the multi-bit flash memory device and to correct data read from the selected memory cells based upon the comparison result.