Abstract: The method for reading data according to example embodiments includes comparing a threshold voltage of a memory cell with a first boundary voltage, comparing the threshold voltage with a second boundary voltage having a higher voltage level than that of the first boundary voltage, and determining data of the memory cell based on the threshold voltage, the first boundary voltage, and the second boundary voltage.

Abstract: A flash memory system includes a multi-bit flash memory device having a memory cell array including memory cells arranged in rows and columns; a read circuit configured to read data from the memory cell array; and control logic configured to control the read circuit so as to successively read data from a selected memory cell and adjacent memory cells to the selected memory cell in response to a request for a read operation with respect to MSB data stored in the selected memory cell. A compare circuit is configured to compare data read from the adjacent memory cells to the selected memory cell provided from the multi-bit flash memory device and to correct data read from the selected memory cells based upon the comparison result.

Abstract: A semiconductor memory device storing multi-bit write data and a related method of verifying data programmed to a memory cell are disclosed. The method compares a write data reference bit selected from the write data with a corresponding external data bit indicative of an intended write data bit value, and verifies a target bit selected from the write data only upon a positive comparison between the write data reference bit and the corresponding external data bit.

Abstract: Provided are a device for reading memory data and a method using the same. The device for reading memory data comprises a memory cell which stores multi-bit information, an information detection unit which detects as much bit information as a predetermined number of bits from among multi-bit information, a source-line voltage control unit which controls a source-line voltage of the memory cell based on the detected bit information from the information detection unit, and a remaining bit information read unit which reads remaining bit information stored in the memory cell by using the controlled source-line voltage.

Abstract: A multi-bit programming device and method for a non-volatile memory are provided. In one example embodiment, a multi-bit programming device may include a multi-bit programming unit configured to multi-bit program original multi-bit data to a target memory cell in a memory cell array, and a backup programming unit configured to select backup memory cells in the memory cell array with respect to each bit of the original multi-bit data, and program each bit of the original multi-bit data to a respective one of the selected backup memory cells.

Abstract: A flash memory device is configured to store multi-bit data on one cell utilizing fewer program operations. The flash memory device includes a memory cell, a sense amplifier and a write driver circuit. The sense amplifier is connected to a word line and a bit line. The sense amplifier and write driver circuit store data bits to be programmed on the memory cell. The sense amplifier and write driver circuit drives the bit line through a program voltage during a program execution period when at least one bit from among the data bits to be programmed is a program data bit, and performs a verify read operation when a program verify code representing a verify read period corresponds to a state of the data bits to be programmed.

Abstract: In one embodiment, the non-volatile memory device includes a plurality of normal memory cells, and at least one flag memory cell associated with one of the plurality of normal memory cells. A normal page buffer is configured to store data read from one of the plurality of normal memory cells. The normal page buffer includes a main latch storing the read data. A control circuit is configured to selectively change data stored in the main latch during a read operation based on a state of the flag memory cell.

Abstract: A non-volatile memory device and method thereof are provided. The example non-volatile memory device may include a plurality of main cells, each of the plurality of main cells arranged at first intersection regions between one of a plurality of word lines and one of a plurality of main bit line pairs and a plurality of flag cells, each of the plurality of flag cells arranged at second intersection regions between one of the plurality of word lines and a plurality of flag bit line pairs, each of the plurality of flag cells configured to store page information in a manner such that page information associated with main cells corresponding to one of the main bit line pairs is stored in flag cells corresponding to more than one of the flag bit line pairs.

Abstract: In one embodiment, the non-volatile memory device includes a plurality of normal memory cells, and at least one flag memory cell associated with one of the plurality of normal memory cells. A normal page buffer is configured to store data read from one of the plurality of normal memory cells. The normal page buffer includes a main latch storing the read data. A control circuit is configured to selectively change data stored in the main latch during a read operation based on a state of the flag memory cell.

Abstract: Provided are a device for reading memory data and a method using the same. The device for reading memory data comprises a memory cell which stores multi-bit information, an information detection unit which detects as much bit information as a predetermined number of bits from among multi-bit information, a source-line voltage control unit which controls a source-line voltage of the memory cell based on the detected bit information from the information detection unit, and a remaining bit information read unit which reads remaining bit information stored in the memory cell by using the controlled source-line voltage.

Abstract: A method is for programming a flash memory device which includes a plurality of memory cells storing multi-bit data representing one of a plurality of states. The method includes programming the multi-bit data into selected memory cells of the plurality of memory cells, the programming including a first verify-reading operation performed by a first verifying voltage, determining whether to execute a reprogramming operation for each of the selected memory cells, and reprogramming the selected memory cells in accordance with the determination. The reprogramming of the selected memory cells includes a second verify-reading operation performed by a second verifying voltage, the second verifying voltage being higher than the first verifying voltage.

Abstract: A semiconductor memory system and access method thereof. The semiconductor memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory stores monitoring data in one or more of plural memory cells. The memory controller controls the nonvolatile memory. The memory controller detects the monitoring data and adjusts a bias voltage, which is provided to the plural memory cells, in accordance with a result of the detection.

Abstract: A read method of a non-volatile memory device includes reading an initial threshold voltage value of an index cell from threshold voltage information cells that store information indicating the initial threshold voltage, determining a current threshold voltage value from the index cell, and comparing the initial threshold voltage value and the current threshold voltage value to calculate a shifted threshold voltage level of the index cell. A read voltage is changed by the shifted threshold voltage level to read user data using the changed read voltage.

Abstract: The flash memory device of the present invention is configured to program a plurality of bits per unit cell, wherein a program condition of a selected bit is set according to whether a program for the most previous bit to the selected bit for programming is skipped or not skipped. As a result, an accurate programming and reading operation is possible even in case a program for a middle bit is skipped.

Abstract: A program method of a flash memory device having first and-second bitlines connected with a plurality of memory cells for storing multi-bit data indicating one of a plurality of states. The program method includes programming memory cells, connected to a selected row and first or second bitlines, with multi-bit data; and reprogramming programmed memory cells connected to a row disposed directly below the selected row and the first bitlines or the second bitlines, whereby increasing a read margin between adjacent states reduced due to high temperature stress (HTS).

Abstract: Provided is a read operation for a N-bit data non-volatile memory system. The method includes determining in relation to data states of adjacent memory cells associated with a selected memory cell in the plurality of memory cells whether read data obtained from the selected memory cell requires compensation, and if the read data requires compensation, replacing the read data with compensated read data.

Abstract: A flash memory system includes a multi-bit flash memory device having a memory cell array including memory cells arranged in rows and columns; a read circuit configured to read data from the memory cell array; and control logic configured to control the read circuit so as to successively read data from a selected memory cell and adjacent memory cells to the selected memory cell in response to a request for a read operation with respect to MSB data stored in the selected memory cell. A compare circuit is configured to compare data read from the adjacent memory cells to the selected memory cell provided from the multi-bit flash memory device and to correct data read from the selected memory cells based upon the comparison result.

Abstract: A flash memory device includes a cell array and a read voltage adjuster. The cell array includes a first field having first memory cells and a second field having second memory cells. The read voltage adjuster determines a read voltage for reading first data from the first memory cells of the first field with reference to second data read from the memory cells of the second field.

Abstract: A method and apparatus for controlling a reading level of a memory cell are provided. The method of controlling a reading level of a memory cell may include: receiving metric values calculated based on given voltage levels and reference levels; generating summed values for each of the reference levels by summing metric values corresponding to levels of a received signal from among the received metric values; selecting the reference level having the greatest value of the generated summed values from the reference levels; and controlling the reading level of the memory cell based on the selected reference level.

Abstract: A program method of a flash memory device including a plurality of memory cells for storing multi-bit data indicating one of states. The program method includes programming memory cells selected to have one of the states by using multi-bit data; detecting programmed memory cells within a predetermined region of a threshold voltage distribution where the programmed memory cells having the respective states are distributed, wherein the predetermined region of the respective states is selected by one of a first verify voltage and a read voltage and a second voltage, the first verify voltage being lower than the second verify voltage and higher than the read voltage; and programming the detected memory cells to have a threshold voltage being equivalent to or higher than the second verify voltage corresponding to each of the states.