Patents by Inventor Dong Kwon

Dong Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170186873
    Abstract: A method of fabricating a semiconductor device is provided as follows. An epitaxial layer is formed on an active fin structure. Metal gate electrodes are formed on the active fin structure. Gate electrode caps are formed on upper surfaces of the metal gate electrodes. Metal gate spacers are formed on sidewalls of the metal gate electrodes. A source/drain electrode is formed on the epitaxial layer. An air spacer region is formed by removing the metal gate electrode caps and the metal gate spacers. An air spacer is formed within the air spacer region.
    Type: Application
    Filed: June 22, 2016
    Publication date: June 29, 2017
    Inventor: DONG-KWON KIM
  • Patent number: 9653571
    Abstract: An aspect of the invention includes a freestanding spacer having a sub-lithographic dimension for a sidewall image transfer process. The freestanding spacer comprises: a first spacer layer having a first portion disposed on the semiconductor layer; and a second spacer layer having a first surface disposed on the first portion of the first spacer layer, wherein the first spacer layer has a first dielectric constant and the second spacer layer has a second dielectric constant, the first dielectric constant being greater than the second dielectric constant, and wherein a dimension of each of the first and second spacer layers collectively determine the sub-lithographic lateral dimension of the freestanding spacer.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: May 16, 2017
    Assignees: International Business Machines Corporation, Samsung Electronics Co., Ltd., GLOBALFOUNDRIES Inc.
    Inventors: Hsueh-Chung Chen, Su Chen Fan, Dong Kwon Kim, Sean Lian, Fee Li Lie, Linus Jang
  • Publication number: 20170117375
    Abstract: A semiconductor device is provided as follows. A first nanowire is disposed on a substrate. The first nanowire is extended in a first direction and spaced apart from the substrate. A gate electrode surrounds a periphery of the first nanowire. The gate electrode is extended in a second direction intersecting the first direction. A gate spacer is formed on a sidewall of the gate electrode. The gate spacer includes an inner sidewall and an outer sidewall facing each other. The inner sidewall of the gate spacer faces the sidewall of the gate electrode. An end portion of the first nanowire is protruded from the outer sidewall of the gate spacer. A source/drain epitaxial layer is disposed on at least one side of the gate electrode. The source/drain is connected to the protruded end portion of the first nanowire.
    Type: Application
    Filed: October 27, 2015
    Publication date: April 27, 2017
    Inventors: Dong-Kwon KIM, Kang-Ill SEO
  • Publication number: 20170117362
    Abstract: A method of fabricating a semiconductor device is provided as follows. A strain relaxed buffer (SRB) layer is formed on a substrate. The SRB layer is formed of a first silicon germanium alloy (SiGe) layer which has a first atomic percent of germanium (Ge) atoms. A heterogeneous channel layer is formed on the SRB layer. The heterogeneous channel layer includes a silicon layer on a first region of the SRB layer and a second SiGe layer on a second region of the SRB layer. The second SiGe layer includes a second atomic percent of germanium greater than the first atomic percent of germanium atoms. The silicon layer is in contact with the second SiGe layer.
    Type: Application
    Filed: May 3, 2016
    Publication date: April 27, 2017
    Inventors: DONG-KWON KIM, JI-HOON CHA
  • Publication number: 20170117363
    Abstract: A method of fabricating a semiconductor device is provided as follows. A channel layer is formed on a strain relaxed buffer (SRB) layer. A first etching process is performed on the channel layer and the SRB layer to form a plurality of trenches. The trenches penetrate through the channel layer and into the SRB layer to a first depth. First liners are formed on first sidewalls of the trenches having the first depth. The first liners cover the first sidewalls. A second etching process is performed on the SRB layer exposed through the trenches. The second etching process is performed on the SRB layer using a gas etchant having etch selectivity with respect to the first liners so that after the performing of the second etching process, the first liners remain on the first sidewalls.
    Type: Application
    Filed: May 3, 2016
    Publication date: April 27, 2017
    Inventors: DONG-KWON KIM, YONG-WOO LEE
  • Patent number: 9627514
    Abstract: A method of fabricating a semiconductor device is provided as follows. Epitaxial layers is formed on an active fin structure of a substrate. First metal gate electrodes are formed on the active fin structure. Each first metal gate electrode and each epitaxial layer are alternately disposed in a first direction on the active fin structure. ILD patterns are formed on the epitaxial layers, extending in a second direction crossing the first direction. Sacrificial spacer patterns are formed on the first metal gate electrodes. Each of the plurality of sacrificial spacer patterns covers a corresponding first metal gate electrode of the first metal gate electrodes. Self-aligned contact holes and sacrificial spacers are formed by removing the ILD patterns. Each self-aligned contact hole exposes a corresponding epitaxial layer disposed under each ILD pattern. Source/drain electrodes are formed in the self-aligned contact holes. The sacrificial spacers are replaced with air spacers.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: April 18, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Kwon Kim, Ji-Hoon Cha
  • Patent number: 9625567
    Abstract: Disclosed is a positioning system using sound waves. The system provides the current location of a user carrying a dedicated terminal or any portable equipment possessing a microphone and a speaker in real time by using sound waves propagating in slow speed in various indoor spaces such as shopping malls, museums, and art galleries where GPS signals are not received.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: April 18, 2017
    Inventor: Dong-Kwon Lim
  • Patent number: 9590038
    Abstract: A semiconductor device is provided as follows. A fin-type pattern includes first and second oxide regions in an upper portion of the fin-type pattern. The fin-type pattern is extended in a first direction. A first nanowire is extended in the first direction and spaced apart from the fin-type pattern. A gate electrode surrounds a periphery of the first nanowire, extending in a second direction intersecting the first direction. The gate electrode is disposed on a region of the fin-type pattern. The region is positioned between the first and the second oxide regions. A first source/drain is disposed on the first oxide region and connected with an end portion of the first nanowire.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: March 7, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Kwon Kim, Kang-Ill Seo
  • Publication number: 20170062245
    Abstract: Provided are substrate processing apparatuses including a temperature measurement unit. The substrate processing apparatus comprises a chamber including a substrate processing region, a dielectric sheet that is disposed on the substrate processing region and includes an insertion hole and a temperature measurement unit that is disposed on the dielectric sheet to measure the temperature of the dielectric sheet, and has a screw portion inserted into the insertion hole, wherein each of the insertion hole and the screw portion has thread helixes meshed with each other.
    Type: Application
    Filed: April 29, 2016
    Publication date: March 2, 2017
    Inventors: Jung-Pyo Hong, Kwang-Nam KIM, Sang-Dong KWON, Jong-Woo SUN, Sang-Rok OH, Yong-Moon JANG
  • Publication number: 20160379886
    Abstract: A method for fabricating a semiconductor device includes forming a pre-fin extending in a first direction, the pre-fin including first, second, and third regions, forming first and second gates on the pre-fin to extend in a second direction intersecting the first direction, the first and second gates being spaced apart from each other in the first direction and overlapping with the first and second regions, respectively, forming first and second dummy spacers on the first and second regions, respectively to form a first trench in the third region that exposes the third region, forming a second trench by etching the exposed third region using the first and second dummy spacers as masks to separate the pre-fin into first and second active fins corresponding to the first and second regions, respectively, forming a dummy gate by filling the first and second trenches and removing the first and second dummy spacers.
    Type: Application
    Filed: June 26, 2015
    Publication date: December 29, 2016
    Inventors: DONG-KWON KIM, KANG-ILL SEO
  • Publication number: 20160365425
    Abstract: An aspect of the invention includes a freestanding spacer having a sub-lithographic dimension for a sidewall image transfer process. The freestanding spacer comprises: a first spacer layer having a first portion disposed on the semiconductor layer; and a second spacer layer having a first surface disposed on the first portion of the first spacer layer, wherein the first spacer layer has a first dielectric constant and the second spacer layer has a second dielectric constant, the first dielectric constant being greater than the second dielectric constant, and wherein a dimension of each of the first and second spacer layers collectively determine the sub-lithographic lateral dimension of the freestanding spacer.
    Type: Application
    Filed: June 15, 2015
    Publication date: December 15, 2016
    Inventors: Hsueh-Chung Chen, Su Chen Fan, Dong Kwon Kim, Sean Lian, Fee Li Lie, Linus Jang
  • Publication number: 20160350108
    Abstract: Embodiments relate to automatically providing textual context for source strings in a source language that are to be translated by a human translator to target strings in a target language. The source strings are compared against a dictionary of reference strings in the source language. For each source string, one or more of the reference strings that are most relevant, similar, etc., are selected. When a human translator is to translate the source strings, the selected reference strings are presented; each source string has one or more similar/related strings displayable in association therewith. For a given source string, the human translator can use the associated reference strings as a form of context to help estimate the intended meaning of the given source string when translating the given source string to a target string in the target language.
    Type: Application
    Filed: May 29, 2015
    Publication date: December 1, 2016
    Inventor: Dong Kwon Joo
  • Patent number: 9508644
    Abstract: A method of forming a pattern includes forming a mask pattern on a substrate; etching the substrate by deep reactive ion etching (DRIE) and by using the mask pattern as an etch mask; partially removing the mask pattern to expose a portion of an upper surface of the substrate; and etching the exposed portion of the upper surface of the substrate. In the method, when a pattern is formed by DRIE, an upper portion of the pattern does not protrude or scarcely protrudes, and scallops of a sidewall of the pattern are smooth, and thus a conformal material layer may be easily formed on a surface of the pattern.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: November 29, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-kwon Kim, Ki-il Kim, Ah-young Cheon, Myeong-cheol Kim, Yong-jin Kim
  • Publication number: 20160321160
    Abstract: In one embodiment, a translation system may use a translation bug prediction model to more efficiently identify translation errors in a user interface text string. The translation system may apply a translation bug prediction model to a translation resource to identify a potential error source. The translation system may associate an attention flag with the translation resource when identified as the potential error source. The translation system may execute an automatic translation of the translation resource to create a translation target.
    Type: Application
    Filed: April 28, 2015
    Publication date: November 3, 2016
    Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Dong Kwon Joo, Kevin O'Donnell
  • Patent number: 9482618
    Abstract: The present invention is to provide a nanoparticle, which can be used effectively for Raman analysis based on very high amplification effect of electromagnetic signal by plasomonic coupling of nanogap formation inside thereof and high reproducibility, and which includes core and surrounding shell with nanogap formation between the same and the method of synthesis thereof. The present invention is also to provide the method for detecting the analyte using the above nanoparticle and the analyte detection kit including the above nanoparticle.
    Type: Grant
    Filed: November 24, 2011
    Date of Patent: November 1, 2016
    Assignees: KOREA RESEARCH INSTITUTE OF CHEMICAL TECHNOLOGY, SNU R&DB FOUNDATION
    Inventors: Yung Doug Suh, Jwa Min Nam, Dong Kwon Lim, Ki Seok Jeon
  • Publication number: 20160314983
    Abstract: A method of forming patterns of a semiconductor device includes sequentially forming first to third mask layers on a substrate including a first region and a second region, etching the third mask layer formed in the first region to form first mask elements of a first mask pattern, etching the third mask layer formed in the second region to form second mask elements of a second mask pattern, forming a first spacer film covering the second mask elements, forming a second spacer film on the first spacer film to fully fill at least one trench between the second mask elements and on the first mask elements, removing portions of the first and second spacer films to expose the upper surfaces of the first and second mask elements, etching the second mask layer, etching the first mask layer, and etching the substrate.
    Type: Application
    Filed: April 22, 2015
    Publication date: October 27, 2016
    Inventors: Eun-Shoo HAN, Dong-Kwon KIM, Bong-Cheol KIM, Kang-ILL SEO
  • Patent number: 9446332
    Abstract: Disclosed is an apparatus for separating gas and liquid. The apparatus for separating gas and liquid includes a housing, a rotating shaft provided inside the housing, a drive unit configured to rotate the rotating shaft, a rotating cone mounted at the rotating shaft to rotate about the rotating shaft and having a diameter decreasing from an upper end to a lower end thereof, a fixed cone fixed in the housing to be spaced apart from the rotating cone and having a diameter decreasing from an upper end to a lower end thereof, and a scraper configured to remove scale generated in at least one of the fixed cone and the rotating cone, based on the rotation of the rotating shaft.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: September 20, 2016
    Assignee: LG Chem, Ltd.
    Inventors: Dae Young Shin, Eun Jung Joo, Dong Kwon Lee, Chang Hoe Heo, Jong Ku Lee
  • Publication number: 20160266104
    Abstract: The present invention relates to a nanoparticle heterodimer in which Raman-active molecules are located at a binding portion of the nanoparticle heterodimer, and more particularly, to a core-shell nanoparticle heterodimer comprising: a gold or silver core having a surface to which oligonucleotides are bonded; and a gold or silver shell covering the core. In addition, the present invention relates to the core-shell nanoparticle dimer, to a method for preparing same, and to the use thereof.
    Type: Application
    Filed: March 14, 2016
    Publication date: September 15, 2016
    Inventors: Yung Doug SUH, Jwa Min NAM, Dong Kwon LIM
  • Patent number: 9434833
    Abstract: Disclosed are a bulk PVC composition and a bulk PVC polymerization method using the same. According to the present invention, a bulk PVC composition that may effectively prevent generation of fine particles and scale (adhering to a reactor wall) during bulk polymerization and may be prepared without a post-treatment process of an antistatic agent added to easily isolate fine particles after bulk PVC polymerization, and a method and apparatus for polymerizing the same may be provided.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: September 6, 2016
    Assignee: LG CHEM, LTD.
    Inventors: Dong Kwon Lee, Kwang Hyon Kim, Bo Hee Park, Se Woong Lee, Jin Hyuck Ju
  • Patent number: 9403144
    Abstract: Disclosed are an apparatus for mass polymerization of a vinyl chloride resin which may suppress generation of abnormal products (fine-particle products, oversize-particle products, lumpy products due to coagulation, etc.) and a vinyl chloride resin, which causes formation of a poor sphere, and may enhance quality and processability of a vinyl chloride resin, by addressing the problem that an average distance between resin particles is decreased as polymerization proceeds, and thus, microparticles are generated due to excessive coagulation or friction between particles, and a method of mass-polymerizing the vinyl chloride resin. The method comprises additionally inputting a monomer to a reactor in which a monomer and an initiator are contained when a ratio of the monomer converted to a polymer is 30% to 70%.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: August 2, 2016
    Assignee: LG CHEM, LTD.
    Inventor: Dong Kwon Lee