Patents by Inventor Dong-Kyun Sohn
Dong-Kyun Sohn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9502413Abstract: A semiconductor device including source drain stressors is provided. The semiconductor device includes a gate structure including a gate insulating layer and a gate electrode on a semiconductor substrate. Gate spacers may be disposed on sidewalls of the gate structure and a stressor pattern including an impurity region is disposed on a side of the gate structure. The stressor pattern includes a protruded portion having a top surface higher than a bottom surface of the gate structure and a facet in the protruded portion. The facet is slanted at a predetermined angle with respect to an upper surface of the semiconductor substrate and forms a concave portion with one of the gate spacers. A blocking insulating layer may extend conformally on the stressor pattern and the gate spacers and an insulating wing pattern is disposed in the concave portion on the blocking insulating layer.Type: GrantFiled: August 17, 2015Date of Patent: November 22, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Se-Chan Lim, Sang-Pil Sim, Dong-Kyun Sohn, Su-Youn Yi
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Patent number: 9425148Abstract: Semiconductor devices, and a method for fabricating the same, include an interlayer dielectric film pattern over a substrate, a first wiring within the interlayer dielectric film pattern and having a first length in a first direction, a second wiring within the interlayer dielectric film pattern and separated from the first wiring, and a spacer contacting the first wiring and the second wiring. The spacer electrically separates the first wiring and the second wiring from each other. The second wiring has a second length different from the first length in the first direction.Type: GrantFiled: December 18, 2012Date of Patent: August 23, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Ho-Jun Kim, Hae-Wang Lee, Chul-Hong Park, Dong-Kyun Sohn, Jong-Shik Yoon
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Publication number: 20150357329Abstract: A semiconductor device including source drain stressors is provided. The semiconductor device includes a gate structure including a gate insulating layer and a gate electrode on a semiconductor substrate. Gate spacers may be disposed on sidewalls of the gate structure and a stressor pattern including an impurity region is disposed on a side of the gate structure. The stressor pattern includes a protruded portion having a top surface higher than a bottom surface of the gate structure and a facet in the protruded portion. The facet is slanted at a predetermined angle with respect to an upper surface of the semiconductor substrate and forms a concave portion with one of the gate spacers. A blocking insulating layer may extend conformally on the stressor pattern and the gate spacers and an insulating wing pattern is disposed in the concave portion on the blocking insulating layer.Type: ApplicationFiled: August 17, 2015Publication date: December 10, 2015Inventors: Se-Chan Lim, Sang-Pil Sim, Dong-Kyun Sohn, Su-Youn Yi
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Patent number: 9147654Abstract: An integrated circuit system that includes: providing a substrate including front-end-of-line circuitry; forming a first conductive level including a first conductive trace over the substrate; forming a second conductive level spaced apart from the first conductive level and including a second conductive trace; and connecting the first conductive level to a third conductive level with a viabar that passes through the second conductive level without contacting the second conductive trace.Type: GrantFiled: July 7, 2008Date of Patent: September 29, 2015Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Haifeng Sheng, Fan Zhang, Juan Boon Tan, Bei Chao Zhang, Dong Kyun Sohn
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Publication number: 20130320457Abstract: A semiconductor device including source drain stressors is provided. The semiconductor device includes a gate structure including a gate insulating layer and a gate electrode on a semiconductor substrate. Gate spacers may be disposed on sidewalls of the gate structure and a stressor pattern including an impurity region is disposed on a side of the gate structure. The stressor pattern includes a protruded portion having a top surface higher than a bottom surface of the gate structure and a facet in the protruded portion. The facet is slanted at a predetermined angle with respect to an upper surface of the semiconductor substrate and forms a concave portion with one of the gate spacers. A blocking insulating layer may extend conformally on the stressor pattern and the gate spacers and an insulating wing pattern is disposed in the concave portion on the blocking insulating layer.Type: ApplicationFiled: June 4, 2013Publication date: December 5, 2013Inventors: Se-Chan Lim, Sang-Pil Sim, Dong-Kyun Sohn, Su-Youn Yi
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Publication number: 20130248990Abstract: Semiconductor devices, and a method for fabricating the same, include an interlayer dielectric film pattern over a substrate, a first wiring within the interlayer dielectric film pattern and having a first length in a first direction, a second wiring within the interlayer dielectric film pattern and separated from the first wiring, and a spacer contacting the first wiring and the second wiring. The spacer electrically separates the first wiring and the second wiring from each other. The second wiring has a second length different from the first length in the first direction.Type: ApplicationFiled: December 18, 2012Publication date: September 26, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ho-Jun KIM, Hae-Wang LEE, Chul-Hong PARK, Dong-Kyun SOHN, Jong-Shik YOON
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Publication number: 20130034954Abstract: An integrated circuit method for manufacturing an integrated circuit system including loading a wafer into a processing chamber and pre-purging the processing chamber with a first ammonia gas. Depositing a first nitride layer over the wafer and purging the processing chamber with a second ammonia gas. Depositing a second nitride layer over the first nitride layer that is misaligned with the first nitride layer. Post-purging the processing chamber with a third ammonia gas and purging the processing chamber with a nitrogen gas.Type: ApplicationFiled: October 8, 2012Publication date: February 7, 2013Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Sripad Sheshagiri Nagarad, Hwa Weng Koh, Dong Kyun Sohn, Xiaoyu Chen, Louis Lim, Sung Mun Jung, Chiew Wah Yap, Pradeep Ramachandramurthy Yelehanka, Nitin Kamat
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Patent number: 8358007Abstract: A method of manufacture of an integrated circuit system includes: fabricating a substrate having an integrated circuit; applying a low-K dielectric layer over the integrated circuit; forming a via and a trench, in the low-K dielectric layer, over the integrated circuit; forming a structure surface by a chemical-mechanical planarization (CMP) process; and applying a direct implant to the structure surface for forming an implant layer and a metal passivation layer including repairing damage, to the low-K dielectric layer, caused by the CMP process.Type: GrantFiled: June 8, 2010Date of Patent: January 22, 2013Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Dong Kyun Sohn, Wuping Liu, Fan Zhang, Juan Boon Tan, Jing Hui Li, Bei Chao Zhang, Luying Du, Wei Liu, Yeow Kheng Lim
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Patent number: 8283263Abstract: An integrated circuit method for manufacturing an integrated circuit system including loading a wafer into a processing chamber and pre-purging the processing chamber with a first ammonia gas. Depositing a first nitride layer over the wafer and purging the processing chamber with a second ammonia gas. Depositing a second nitride layer over the first nitride layer that is misaligned with the first nitride layer. Post-purging the processing chamber with a third ammonia gas and purging the processing chamber with a nitrogen gas.Type: GrantFiled: July 5, 2006Date of Patent: October 9, 2012Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Sripad Sheshagiri Nagarad, Hwa Weng Koh, Dong Kyun Sohn, Xiaoyu Chen, Louis Lim, Sung Mun Jung, Chiew Wah Yap, Pradeep Ramachandramurthy Yelehanka, Nitin Kamat
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Patent number: 8034670Abstract: A method of forming a semiconductor device is presented. A substrate prepared with a second gate is provided. The second gate is processed to form a second gate with a rounded corner and a first gate is formed on the substrate. The first gate is adjacent to and overlaps a portion of the second gate and the rounded corner.Type: GrantFiled: March 11, 2009Date of Patent: October 11, 2011Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Timothy Phua, Bangun Indajang, Dong Kyun Sohn
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Patent number: 8008744Abstract: A first example embodiment comprises the following steps and the structure formed therefrom. A trench having opposing sidewalls is formed within a substrate. A stress layer having an inherent stress is formed over the opposing trench sidewalls. The stress layer having stress layer sidewalls over the trench sidewalls. Ions are implanted into one or more portions of the stress layer to form ion-implanted relaxed portions with the portions of the stress layer that are not implanted are un-implanted portions, whereby the inherent stress of the one or more ion-implanted relaxed portions of stress layer portions is relaxed.Type: GrantFiled: May 31, 2010Date of Patent: August 30, 2011Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Lee Wee Teo, Shiang Yang Ong, Jae Gon Lee, Vincent Leong, Elgin Quek, Dong Kyun Sohn
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Patent number: 7888214Abstract: A structure and method of fabrication of a semiconductor device, where a stress layer is formed over a MOS transistor to put either tensile stress or compressive stress on the channel region. The parameters such as the location and area of the contact hole thru the stress layer are chosen to produce a desired amount of stress to improve device performance. In an example embodiment for a tensile stress layer, the PMOS S/D contact area is larger than the NMOS S/D contact area so the tensile stress on the PMOS channel is less than the tensile stress on the NMOS channel. In an example embodiment for a compressive stress layer, the NMOS contact area is larger than the PMOS contact area so that the compressive stress on the NMOS channel is less than the compressive stress on the PMOS channel.Type: GrantFiled: December 13, 2005Date of Patent: February 15, 2011Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Lee Wee Teo, Elgin Quek, Dong Kyun Sohn
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Publication number: 20100314763Abstract: A method of manufacture of an integrated circuit system includes: fabricating a substrate having an integrated circuit; applying a low-K dielectric layer over the integrated circuit; forming a via and a trench, in the low-K dielectric layer, over the integrated circuit; forming a structure surface by a chemical-mechanical planarization (CMP) process; and applying a direct implant to the structure surface for forming an implant layer and a metal passivation layer including repairing damage, to the low-K dielectric layer, caused by the CMP process.Type: ApplicationFiled: June 8, 2010Publication date: December 16, 2010Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Dong Kyun Sohn, Wuping Liu, Fan Zhang, Juan Boon Tan, Jing Hui Li, Bei Chao Zhang, Luying Du, Wei Liu, Yeow Kheng Lim
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Publication number: 20100230777Abstract: A first example embodiment comprises the following steps and the structure formed therefrom. A trench having opposing sidewalls is formed within a substrate. A stress layer having an inherent stress is formed over the opposing trench sidewalls. The stress layer having stress layer sidewalls over the trench sidewalls. Ions are implanted into one or more portions of the stress layer to form ion-implanted relaxed portions with the portions of the stress layer that are not implanted are un-implanted portions, whereby the inherent stress of the one or more ion-implanted relaxed portions of stress layer portions is relaxed.Type: ApplicationFiled: May 31, 2010Publication date: September 16, 2010Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Lee Wee TEO, Shiang Yang ONG, Jae Gon LEE, Vincent LEONG, Elgin QUEK, Dong Kyun SOHN
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Publication number: 20100230744Abstract: A method of forming a semiconductor device is presented. A substrate prepared with a second gate is provided. The second gate is processed to form a second gate with a rounded corner and a first gate is formed on the substrate. The first gate is adjacent to and overlaps a portion of the second gate and the rounded corner.Type: ApplicationFiled: March 11, 2009Publication date: September 16, 2010Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Timothy Phua, Bangun Indajang, Dong Kyun Sohn
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Patent number: 7727856Abstract: A first example embodiment comprises the following steps and the structure formed therefrom. A trench having opposing sidewalls is formed within a substrate. A stress layer having an inherent stress is formed over the opposing trench sidewalls. The stress layer having stress layer sidewalls over the trench sidewalls. Ions are implanted into one or more portions of the stress layer to form ion-implanted relaxed portions with the portions of the stress layer that are not implanted are un-implanted portions, whereby the inherent stress of the one or more ion-implanted relaxed portions of stress layer portions is relaxed.Type: GrantFiled: December 24, 2006Date of Patent: June 1, 2010Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Lee Wee Teo, Shiang Yang Ong, Jae Gon Lee, Vincent Leong, Elgin Quek, Dong Kyun Sohn
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Patent number: 7645687Abstract: An embodiment of fabrication of a variable work function gates in a FUSI device is described. The embodiment uses a work function doping implant to dope the polysilicon to achieve a desired work function. Selective epitaxy growth (SEG) is used to form silicon over the source/drain regions. The doped poly-Si gate is fully silicided to form fully silicided gates that have a desired work function. We provide a substrate having a NMOS region and a PMOS region. We form a gate dielectric layer and a gate layer over said substrate. We perform a (gate Vt) gate layer implant process to implant impurities such as P+, As+, B+, BF2+, N+, Sb+, In+, C+, Si+, Ge+ or Ar+ into the gate layer gate in the NMOS gate regions and said PMOS gate regions. We form a cap layer over said gate layer. We pattern said cap layer, said gate layer and said gate dielectric layer to form a NMOS gate and a PMOS gate. Spacers are formed and S/D regions are formed. A metal is deposited over said substrate surface.Type: GrantFiled: January 20, 2005Date of Patent: January 12, 2010Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Yung Fu Chong, Dong Kyun Sohn, Chew-Hue Ang, Purakh Raj Vermo, Liang Choo Hsia
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Publication number: 20100001370Abstract: An integrated circuit system that includes: providing a substrate including front-end-of-line circuitry; forming a first conductive level including a first conductive trace over the substrate; forming a second conductive level spaced apart from the first conductive level and including a second conductive trace; and connecting the first conductive level to a third conductive level with a viabar that passes through the second conductive level without contacting the second conductive trace.Type: ApplicationFiled: July 7, 2008Publication date: January 7, 2010Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Haifeng Sheng, Fan Zhang, Juan Boon Tan, Bei Chao Zhang, Dong Kyun Sohn
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Patent number: 7585746Abstract: In an non-limiting example, we provide a substrate having a cell region, and non-cell regions. We form a tunneling dielectric layer, a charge storing layer, a top insulating layer (e.g., ONO), over the substrate. Then we form a conductive pad layer over the top insulating layer. We form isolation trenches in the pad layer, the charge storing layer and the tunneling dielectric layer and into the substrate. We form isolation regions in the isolation trenches. We remove the pad layer, charge storing layer and the tunneling dielectric layer in the non-cell regions. We form a gate layer over the pad layer and the substrate surface. We complete to form the memory (e.g., SONOS) device in the cell region and other devices in the non-cell regions of the substrate.Type: GrantFiled: July 12, 2006Date of Patent: September 8, 2009Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Sung Mun Jung, Yoke Leng Louis Lim, Sripad Nagarad, Dong Kyun Sohn, Dong Hua Liu, Xiao Yu Chen, Rachel Low
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Publication number: 20090023280Abstract: Structures and methods of fabricating of a floating gate non-volatile memory device. In a first example embodiment, We form a bottom tunnel layer comprised of a lower oxide tunnel layer and a upper hafnium oxide tunnel layer; a charge storage layer comprised of a tantalum oxide and a top blocking layer preferably comprised of a lower hafnium oxide storage layer and an upper oxide storage layer. We form a gate electrode over the top blocking layer. We pattern the layers to form a gate structure and form source/drain regions to complete the memory device. In a second example embodiment, we form a floating gate non-volatile memory device comprised of: a bottom tunnel layer comprised essentially of silicon oxide; a charge storage layer comprised of a tantalum oxide; a top blocking layer comprised essentially of silicon oxide; and a gate electrode. The embodiments also comprise anneals and nitridation steps.Type: ApplicationFiled: October 1, 2008Publication date: January 22, 2009Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Chew-Hoe ANG, Dong Kyun SOHN, Liang Choo HSIA