Patents by Inventor Dong-myung Choi
Dong-myung Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140242453Abstract: An electrolyte for a rechargeable lithium battery including a lithium salt, a non-aqueous organic solvent, and an additive, wherein the additive includes a compound represented by Chemical Formula 1 and a rechargeable lithium battery including the same.Type: ApplicationFiled: January 23, 2014Publication date: August 28, 2014Applicant: Samsung SDI Co., Ltd.Inventors: Seung-Tae Lee, Jung-Yi Yu, Woo-Cheol Shin, Sang-Il Han, Sang-Hoon Kim, Byung-Joo Chung, Duck-Hyun Kim, Myung-Hwan Jeong, Tae-Hyun Bae, Mi-Hyun Lee, Eon-Mi Lee, Ha-Rim Lee, Moon-Sung Kim, In-Haeng Cho, E-Rang Cho, Dong-Myung Choi, Vladimir Egorov, Makhmut Khasanov, Pavel Alexandrovich Shatunov, Alexey Tereshchenko, Denis Chernyshov
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Publication number: 20140220426Abstract: A phosphorous containing compound represented by the following Chemical Formula 1, a method of preparing the phosphorous containing compound, an electrolyte for a rechargeable lithium battery including the phosphorous containing compound, and a rechargeable lithium battery including the electrolyte. (R1O)2P(NR2R3).Type: ApplicationFiled: August 27, 2013Publication date: August 7, 2014Applicant: Samsung SDI Co., Ltd.Inventors: Denis Chernyshov, Woo-Cheol Shin, Vladimir Egorov, Pavel Alexandrovich Shatunov, Alexey Tereshchenko, Makhmut Khasanov, Jung-Yi Yu, Sang-IL Han, Sang-Hoon Kim, Duck-Hyun Kim, Myung-Hwan Jeong, Seung-Tae Lee, Tae-Hyun Bae, Mi-Hyun Lee, Eon-Mi Lee, Ha-Rim Lee, Moon-Sung Kim, In-Haeng Cho, E-Rang Cho, Dong-Myung Choi
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Publication number: 20140210656Abstract: A processor and a circuit implementing a continuous-time deglitching technique for a digital-to-analog converter are disclosed. The circuit includes a digital-to-analog converter having a differential current output, an operational amplifier having an inverting input coupled to a first output of the differential current output and a non-inverting input coupled to a second output of the differential current output, and a transistor coupled to the second output and the output of the operational amplifier. The operational amplifier is configured to operate the transistor to adjust the voltage potential of the second output to substantially match the voltage potential of the first output.Type: ApplicationFiled: January 30, 2013Publication date: July 31, 2014Applicant: NVIDIA CorporationInventors: Dong-Myung Choi, Anuradha Subbaraman
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Patent number: 8786478Abstract: A processor and a circuit implementing a continuous-time deglitching technique for a digital-to-analog converter are disclosed. The circuit includes a digital-to-analog converter having a differential current output, an operational amplifier having an inverting input coupled to a first output of the differential current output and a non-inverting input coupled to a second output of the differential current output, and a transistor coupled to the second output and the output of the operational amplifier. The operational amplifier is configured to operate the transistor to adjust the voltage potential of the second output to substantially match the voltage potential of the first output.Type: GrantFiled: January 30, 2013Date of Patent: July 22, 2014Assignee: NVIDIA CorporationInventors: Dong-Myung Choi, Anuradha Subbaraman
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Publication number: 20140134479Abstract: An electrolyte additive represented by the following Chemical Formula 1, an electrolyte, and a rechargeable lithium battery are disclosed: In Chemical Formula 1, R1 to R3 and L1 to L3 are the same as defined in the detailed description.Type: ApplicationFiled: March 13, 2013Publication date: May 15, 2014Applicant: Samsung SDI Co., Ltd.Inventors: DUCK-HYUN KIM, WOO-CHEOL SHIN, SANG-IL HAN, SANG-HOON KIM, BYUNG-JOO CHUNG, MYUNG-HWAN JEONG, JUNG-YI YU, JUNG-HYUN NAM, SEUNG-TAE LEE, TAE-HYUN BAE, MI-HYUN LEE, EON-MI LEE, HA-RIM LEE, MOON-SUNG KIM, IN-HAENG CHO, E-RANG CHO, DONG-MYUNG CHOI, VLADIMIR EGOROV, MAKHMUT KHASANOV, PAVEL SHATUNOV, ALEXEY TERESHCHENKO, DENIS CHERNYSHOV
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Patent number: 7835205Abstract: A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow for a broad frequency range of operation, fast locking time over a wide range of input clock frequencies, and a lower current consumption at high clock frequencies. Better performance is achieved by allowing the number of analog delay stages active during a given operation to be flexibly set. The deactivation or turning off of unused delay stages conserves power at higher frequencies. The high frequency range of operation is increased by using a flexible number of delay stages for various input clock frequencies. Because of the rules governing abstracts, this abstract should not be used to construe the claims.Type: GrantFiled: October 16, 2008Date of Patent: November 16, 2010Assignee: Micron Technology, Inc.Inventors: Kang Yong Kim, Dong Myung Choi
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Patent number: 7728637Abstract: A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase detector, which compares the phase of the output clock signal to the phase of the input clock signal. The output clock signal is generated by a voltage controlled oscillator having a control input coupled to receive an output from the phase detector, and a frequency multiplier coupled to the output of the voltage controlled oscillator. As a result, the CLKOUT signal generated by the frequency multiplier has a relatively high frequency while the voltage controlled oscillator, by operating at a relatively low frequency, uses relatively little power.Type: GrantFiled: October 6, 2008Date of Patent: June 1, 2010Assignee: Round Rock Research, LLCInventor: Dong Myung Choi
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Publication number: 20090066379Abstract: A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow for a broad frequency range of operation, fast locking time over a wide range of input clock frequencies, and a lower current consumption at high clock frequencies. Better performance is achieved by allowing the number of analog delay stages active during a given operation to be flexibly set. The deactivation or turning off of unused delay stages conserves power at higher frequencies. The high frequency range of operation is increased by using a flexible number of delay stages for various input clock frequencies. Because of the rules governing abstracts, this abstract should not be used to construe the claims.Type: ApplicationFiled: October 16, 2008Publication date: March 12, 2009Inventors: Kang Yong Kim, Dong Myung Choi
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Publication number: 20090039928Abstract: A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase detector, which compares the phase of the output clock signal to the phase of the input clock signal. The output clock signal is generated by a voltage controlled oscillator having a control input coupled to receive an output from the phase detector, and a frequency multiplier coupled to the output of the voltage controlled oscillator. As a result, the CLKOUT signal generated by the frequency multiplier has a relatively high frequency while the voltage controlled oscillator, by operating at a relatively low frequency, uses relatively little power.Type: ApplicationFiled: October 6, 2008Publication date: February 12, 2009Applicant: Micron Technology, Inc.Inventor: Dong Myung Choi
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Patent number: 7489568Abstract: A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow for a broad frequency range of operation, fast locking time over a wide range of input clock frequencies, and a lower current consumption at high clock frequencies. Better performance is achieved by allowing the number of analog delay stages active during a given operation to be flexibly set. The deactivation or turning off of unused delay stages conserves power at higher frequencies. The high frequency range of operation is increased by using a flexible number of delay stages for various input clock frequencies. Because of the rules governing abstracts, this abstract should not be used to construe the claims.Type: GrantFiled: December 8, 2005Date of Patent: February 10, 2009Assignee: Micron Technology, Inc.Inventors: Kang Yong Kim, Dong Myung Choi
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Patent number: 7447106Abstract: A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow for a broad frequency range of operation, fast locking time over a wide range of input clock frequencies, and a lower current consumption at high clock frequencies. Better performance is achieved by allowing the number of analog delay stages active during a given operation to be flexibly set. The deactivation or turning off of unused delay stages conserves power at higher frequencies. The high frequency range of operation is increased by using a flexible number of delay stages for various input clock frequencies. Because of the rules governing abstracts, this abstract should not be used to construe the claims.Type: GrantFiled: December 8, 2005Date of Patent: November 4, 2008Assignee: Micron Technology, Inc.Inventors: Kang Yong Kim, Dong Myung Choi
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Patent number: 7436231Abstract: A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase detector, which compares the phase of the output clock signal to the phase of the input clock signal. The output clock signal is generated by a voltage controlled oscillator having a control input coupled to receive an output from the phase detector, and a frequency multiplier coupled to the output of the voltage controlled oscillator. As a result, the CLKOUT signal generated by the frequency multiplier has a relatively high frequency while the voltage controlled oscillator, by operating at a relatively low frequency, uses relatively little power.Type: GrantFiled: March 9, 2007Date of Patent: October 14, 2008Assignee: Micron Technology, Inc.Inventor: Dong Myung Choi
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Patent number: 7391243Abstract: A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase detector, which compares the phase of the output clock signal to the phase of the input clock signal. The output clock signal is generated by a voltage controlled oscillator having a control input coupled to receive an output from the phase detector, and a frequency multiplier coupled to the output of the voltage controlled oscillator. As a result, the CLKOUT signal generated by the frequency multiplier has a relatively high frequency while the voltage controlled oscillator, by operating at a relatively low frequency, uses relatively little power.Type: GrantFiled: April 18, 2007Date of Patent: June 24, 2008Assignee: Micron Technology, Inc.Inventor: Dong Myung Choi
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Patent number: 7382678Abstract: A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow for a broad frequency range of operation, fast locking time over a wide range of input clock frequencies, and a lower current consumption at high clock frequencies. Better performance is achieved by allowing the number of analog delay stages active during a given operation to be flexibly set. The deactivation or turning off of unused delay stages conserves power at higher frequencies. The high frequency range of operation is increased by using a flexible number of delay stages for various input clock frequencies. Because of the rules governing abstracts, this abstract should not be used to construe the claims.Type: GrantFiled: December 8, 2005Date of Patent: June 3, 2008Assignee: Micron Technology, Inc.Inventors: Kang Yong Kim, Dong Myung Choi
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Patent number: 7345515Abstract: A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase detector, which compares the phase of the output clock signal to the phase of the input clock signal. The output clock signal is generated by a voltage controlled oscillator having a control input coupled to receive an output from the phase detector, and a frequency multiplier coupled to the output of the voltage controlled oscillator. As a result, the CLKOUT signal generated by the frequency multiplier has a relatively high frequency while the voltage controlled oscillator, by operating at a relatively low frequency, uses relatively little power.Type: GrantFiled: March 9, 2007Date of Patent: March 18, 2008Assignee: Micron Technology, Inc.Inventor: Dong Myung Choi
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Patent number: 7276945Abstract: A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase detector, which compares the phase of the output clock signal to the phase of the input clock signal. The output clock signal is generated by a voltage controlled oscillator having a control input coupled to receive an output from the phase detector, and a frequency multiplier coupled to the output of the voltage controlled oscillator. As a result, the CLKOUT signal generated by the frequency multiplier has a relatively high frequency while the voltage controlled oscillator, by operating at a relatively low frequency, uses relatively little power.Type: GrantFiled: March 31, 2006Date of Patent: October 2, 2007Assignee: Micron Technology, Inc.Inventor: Dong Myung Choi
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Patent number: 7236028Abstract: A delay-locked loop circuit receiving an input clock signal and generating an output clock signal whose delay is locked to the input clock includes a voltage controlled delay line (VCDL), a multiplexer, a phase detection control loop and a phase selection control loop. The VCDL generates a set of multi-phase delayed clock signals. The multiplexer selects one of the delayed clock signals as the output clock signal based on a select signal. The phase detection control loop measures the phase difference between the input and output clock signals and generate a control voltage for driving the VCDL. The phase selection control loop measures the control voltage and generates the select signal based on the control voltage, causing the multiplexer to select a delayed clock signal with increased or decreased amount of phase delay relative to the currently selected delayed clock signal or to hold the currently selected delayed clock signal.Type: GrantFiled: July 22, 2005Date of Patent: June 26, 2007Assignee: National Semiconductor CorporationInventor: Dong-Myung Choi
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Patent number: 7149145Abstract: A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow for a broad frequency range of operation, fast locking time over a wide range of input clock frequencies, and a lower current consumption at high clock frequencies. Better performance is achieved by allowing the number of analog delay stages active during a given operation to be flexibly set. The deactivation or turning off of unused delay stages conserves power at higher frequencies. The high frequency range of operation is increased by using a flexible number of delay stages for various input clock frequencies. Because of the rules governing abstracts, this abstract should not be used to construe the claims.Type: GrantFiled: July 19, 2004Date of Patent: December 12, 2006Assignee: Micron Technology, Inc.Inventors: Kang Yong Kim, Dong Myung Choi
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Patent number: 7042260Abstract: A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase detector, which compares the phase of the output clock signal to the phase of the input clock signal. The output clock signal is generated by a voltage controlled oscillator having a control input coupled to receive an output from the phase detector, and a frequency multiplier coupled to the output of the voltage controlled oscillator. As a result, the CLKOUT signal generated by the frequency multiplier has a relatively high frequency while the voltage controlled oscillator, by operating at a relatively low frequency, uses relatively little power.Type: GrantFiled: June 14, 2004Date of Patent: May 9, 2006Assignee: Micron Technology, Inc.Inventor: Dong Myung Choi
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Patent number: 6542041Abstract: A phase locked loop (PLL) and method for stable clock generation in applications of wide band channel clock recovery performs frequency detection and phase detection with respect to an eight to fourteen modulation (EFM) signal and a PLL clock signal, and adjusts the current based on the results of the frequency detection and the phase detection, thereby generating the PLL clock signal synchronized with the EFM signal. The PLL includes a charge pump, a first low-pass filter, a voltage controlled oscillator and a static phase error controller. The charge pump sources or sinks the current in response to the results of the frequency detection and the phase detection and outputs the result of sourcing or sinking the current. The first low-pass filter low-pass filters the signal output from the charge pump and outputs the filtered result as a direct current control voltage.Type: GrantFiled: January 24, 2001Date of Patent: April 1, 2003Assignee: Samsung Electronics Co., Ltd.Inventor: Dong-myung Choi