Abstract: A phase locked loop (PLL) and method for stable clock generation in applications of wide band channel clock recovery performs frequency detection and phase detection with respect to an eight to fourteen modulation (EFM) signal and a PLL clock signal, and adjusts the current based on the results of the frequency detection and the phase detection, thereby generating the PLL clock signal synchronized with the EFM signal. The PLL includes a charge pump, a first low-pass filter, a voltage controlled oscillator and a static phase error controller. The charge pump sources or sinks the current in response to the results of the frequency detection and the phase detection and outputs the result of sourcing or sinking the current. The first low-pass filter low-pass filters the signal output from the charge pump and outputs the filtered result as a direct current control voltage.

Abstract: A charge pump systematically compensating for the deviation of output pumping current is provided. In the charge pump, a first current source supplies first current of the same level through first and second channels, and a second current source supplies second current of the same level through third and fourth channels. First switching means is connected between the first channel of the first current source and an output node, and is turned on in response to the first signal from a phase detector to output the first current as the first pumping current through the output node. Second switching means is connected between the output node and the third channel of the second current source, and is turned on in response to the second signal from the phase detector to output the second current as the second pumping current through the output node.

Abstract: A method and phase locked loop for generating an eight-to-fourteen (EFM) data restoring clock signal. A frequency detector detects the number of clock pulses input during a pulse width of the EFM data signal, compares the detected number with predetermined maximum and minimum values, and outputs a signal indicative of the resulting comparison value. A voltage controlled oscillator varies an oscillating frequency in response to a DC control signal and outputs the clock pulses corresponding to the oscillating frequency. A programmable counter frequency-divides the clock pulses generated by the voltage controlled oscillator in response to a predetermined speed multiple and outputs the frequency-divided clock pulses. A phase detector detects a phase difference between the EFM data signal and the clock pulses generated by the programmable counter and outputs a signal indicative of the phase difference. A mixer mixes the output of the phase detector with the output of the frequency detector.