Abstract: A memory device performs first training including a plurality of loop operations to align a main clock signal and a data clock signal, which are received from a memory controller. A method of operating the memory device includes generating division ratio information indicating a division ratio set based on a frequency ratio of the main clock signal to the data clock signal and transmitting the division ratio information to the memory controller to perform the first training.

Abstract: A magnetic random access memory (MRAM), and a memory module, memory system including the same, and method for controlling the same are disclosed. The MRAM includes magnetic memory cells configured to change between at least two states according to a magnetization direction, and a mode register supporting a plurality of operational modes.

Abstract: A memory device includes an output pin, a mode register, a signal generator configured to generate a detection clock output signal including one of a random data pattern and a hold data pattern in response to first and second control signals from the mode register, and output the detection clock output signal through the output pin. The random data pattern includes pseudo-random data generated by the memory device. The hold data pattern is a fixed pattern pre stored in the memory device. The detection clock output signal is used for a clock and data recovery operation.

Abstract: A plasma stabilization method and a deposition method using the same are disclosed. The plasma stabilization method includes (a) supplying a source gas and (b) supplying a purge gas. The method may also include (c) supplying a reactive gas and (d) supplying plasma. The purge gas and the reactive gas are continuously supplied into a reactor during (a) through (d), and the plasma stabilization method is performed in a state where no substrate exists in the reactor.

Abstract: A memory device includes an internal clock generator, a deserializer, a data comparator, and a clock controller. The internal clock generator generates a plurality of internal clock signals, which have different phases from each other, by dividing a clock signal received from a host. The deserializer deserializes serial test data received from a host as pieces of internal data using the internal clock signals. The data comparator compares reference data with the internal data. The clock controller corrects a clock dividing start time point of the clock signal of the internal clock generator based on the result of the comparison of the reference data and the internal data.

Abstract: Disclosed is a method of depositing a thin film, which includes supplying a purge gas and a source gas into a plurality of reactors for a first period, stopping supplying of the source gas, and supplying the purge gas and a reaction gas into the plurality of reactors for a second period, and supplying the reaction gas and plasma into the plurality of reactors for a third period.

Abstract: A substrate supporting plate that may prevent deposition on a rear surface of a substrate and may easily unload the substrate. The substrate supporting plate may include a substrate mounting portion and a peripheral portion surrounding the substrate mounting portion. An edge portion of a top surface of the substrate mounting portion may be anodized. A central portion of the top surface of the substrate mounting portion may not be anodized.

Abstract: A plasma stabilization method and a deposition method using the same are disclosed. The plasma stabilization method includes (a) supplying a source gas and (b) supplying a purge gas. The method may also include (c) supplying a reactive gas and (d) supplying plasma. The purge gas and the reactive gas are continuously supplied into a reactor during (a) through (d), and the plasma stabilization method is performed in a state where no substrate exists in the reactor.

Abstract: A method of depositing a thin film includes: supplying a first source gas to a reactor during a first time period; supplying a purge gas to the reactor during a second time period; supplying a second source gas to the reactor during a third time period; and supplying the purge gas to the reactor during a fourth time period, wherein the first source gas and the second source gas comprise polymer precursors, and wherein the first source gas and the second source gas are supplied at a temperature that is less than 100° C. or about 100° C. According to the method, uniformity and step coverage of a thin film can be improved by depositing an amorphous carbon layer using polymer precursors according to an Atomic layer deposition (ALD) method.

Abstract: A method for forming a silicon germanium oxide thin film on a substrate in a reaction space may be performed using an atomic layer deposition (ALD) process. The process may include at least one cycle comprising a germanium oxide deposition sub-cycle and a silicon oxide deposition sub-cycle. The germanium oxide deposition sub-cycle may include contacting the substrate with a germanium reactant, removing excess germanium reactant, and contacting the substrate with a first oxygen reactant. The silicon oxide deposition sub-cycle may include contacting the substrate with a silicon reactant, removing excess silicon reactant, and contacting the substrate with a second oxygen reactant. The films of the present disclosure exhibit desirable etch rates relative to thermal oxide. Depending on the films' composition, the etch rates may be higher or lower than the etch rates of thermal oxide.

Abstract: A method of depositing a thin film includes: supplying a first source gas to a reactor during a first time period; supplying a purge gas to the reactor during a second time period; supplying a second source gas to the reactor during a third time period; and supplying the purge gas to the reactor during a fourth time period, wherein the first source gas and the second source gas comprise polymer precursors, and wherein the first source gas and the second source gas are supplied at a temperature that is less than 100° C. or about 100° C. According to the method, uniformity and step coverage of a thin film can be improved by depositing an amorphous carbon layer using polymer precursors according to an Atomic layer deposition (ALD) method.

Abstract: Disclosed is a current sense amplifier suitable for a nonvolatile memory device such as a magnetic random access memory. In the current sense amplifier, a reference memory cell for sensing is implemented by a memory cell equal to a normal memory cell without fabricating different reference memory cells. The current sense amplifier is formed of first and second cross coupled differential amplifiers being covalent bonded. The current sense amplifier compares a current flowing to a sensing node of a memory cell directly with currents flowing to reference sensing nodes.

Abstract: A semiconductor memory device includes a cell array including one or more bank groups, where each of the one or more bank groups includes a plurality of banks and each of the plurality of banks includes a plurality of spin transfer torque magneto resistive random access memory (STT-MRAM) cells. The semiconductor memory device further includes a source voltage generating unit for applying a voltage to a source line connected to the each of the plurality of STT-MRAM cells, and a command decoder for decoding a command from an external source in order to perform read and write operations on the plurality of STT-MRAM cells. The command includes a combination of at least one signal of a row address strobe (RAS), a column address strobe (CAS), a chip selecting signal (CS), a write enable signal (WE), and a clock enable signal (CKE).

Abstract: A semiconductor memory device includes a memory cell array, a mode register set and a test circuit. The memory cell array includes a plurality of wordlines, a plurality of bitlines, and a plurality of spin-transfer torque magneto-resistive random access memory (STT-MRAM) cells, and each STT-MRAM cell disposed in a cross area of each wordline and bitline, and the STT-MRAM cell includes a magnetic tunnel junction (MTJ) element and a cell transistor. A gate of the cell transistor is coupled to a wordline, a first electrode of the cell transistor is coupled to a bitline via the MTJ element, and a second electrode of the cell transistor is coupled to a source line. The mode register set is configured to set a test mode, and the test circuit is configured to perform a test operation by using the mode register set.

Abstract: Disclosed is a method of depositing a thin film, which includes supplying a purge gas and a source gas into a plurality of reactors for a first period, stopping supplying of the source gas, and supplying the purge gas and a reaction gas into the plurality of reactors for a second period, and supplying the reaction gas and plasma into the plurality of reactors for a third period.

Abstract: Disclosed is a current sense amplifier suitable for a nonvolatile memory device such as a magnetic random access memory. In the current sense amplifier, a reference memory cell for sensing is implemented by a memory cell equal to a normal memory cell without fabricating different reference memory cells. The current sense amplifier is formed of first and second cross coupled differential amplifiers being covalent bonded. The current sense amplifier compares a current flowing to a sensing node of a memory cell directly with currents flowing to reference sensing nodes.

Abstract: A memory cell array of a nonvolatile semiconductor memory device is provided which includes a first memory cell including a first variable resistance element and a first access transistor connected to each other, and having a first node connected to a first bit line and one end of the first variable resistance element and a second node connected to a second bit line and one end of the first access transistor; and a second memory cell including a second variable resistance element and a second access transistor connected to each other, and having a first node connected to the second bit line and one end of the second variable resistance element and a second node connected to one end of the second access transistor, wherein the first and second access transistors are connected to first and second word lines, respectively.

Abstract: A method of controlling a read operation of a resistive memory device is provided which includes activating at least one of a plurality of word lines in response to a first command; after receiving a second command, sensing data of a memory cell, corresponding to a selected page, from among all memory cells connected with the activated word line through a corresponding bit line sense amplifier; and outputting the sensed data as read data according to a sensing output control signal.

Abstract: A method for forming a silicon germanium oxide thin film on a substrate in a reaction space may be performed using an atomic layer deposition (ALD) process. The process may include at least one cycle comprising a germanium oxide deposition sub-cycle and a silicon oxide deposition sub-cycle. The germanium oxide deposition sub-cycle may include contacting the substrate with a germanium reactant, removing excess germanium reactant, and contacting the substrate with a first oxygen reactant. The silicon oxide deposition sub-cycle may include contacting the substrate with a silicon reactant, removing excess silicon reactant, and contacting the substrate with a second oxygen reactant. The films of the present disclosure exhibit desirable etch rates relative to thermal oxide. Depending on the films' composition, the etch rates may be higher or lower than the etch rates of thermal oxide.

Abstract: A semiconductor memory device includes a memory cell array, a mode register set and a test circuit. The memory cell array includes a plurality of wordlines, a plurality of bitlines, and a plurality of spin-transfer torque magneto-resistive random access memory (STT-MRAM) cells, and each STT-MRAM cell disposed in a cross area of each wordline and bitline, and the STT-MRAM cell includes a magnetic tunnel junction (MTJ) element and a cell transistor. The MTJ element includes a free layer, a barrier layer and a pinned layer. A gate of the cell transistor is coupled to a wordline, a first electrode of the cell transistor is coupled to a bitline via the MTJ element, and a second electrode of the cell transistor is coupled to a source line. The mode register set is configured to set a test mode, and the test circuit is configured to perform a test operation by using the mode register set.