Abstract: Disclosed herein is a mounting structure of a circuit board having a multi-layered ceramic capacitor thereon, the multi-layered ceramic capacitor including dielectric sheets laminated thereon and external terminal electrodes formed at both ends thereof, the dielectric sheets having internal electrodes formed thereon, and the external terminal electrodes being connected in parallel with the internal electrode, wherein the internal electrodes are disposed to be in parallel with the circuit board, the external terminal electrodes are bonded to lands of the circuit board by a conductive material, and a bonding height (Ts) of the conductive material is lower than a sum of a gap (Ta) between the circuit board and a bottom surface of the multi-layered ceramic capacitor and a thickness (Tc) of a cover layer on a lower portion of the multi-layered ceramic capacitor, whereby vibration noise can be greatly reduced.

Abstract: A method of fabricating an LCD device is discussed. The method according to an embodiment includes combining a first substrate having thin film transistors with a second substrate having black matrices and color filters using a sealant. Also, the method includes: forming an absorbent layer which is positioned to overlap with an edge of the sealant and burned by a laser; curing the sealant partially covered with the absorbent layer by irradiating UV light; burning the absorbent layer using a laser beam; and cutting the sealant through the burnt absorbent layer and the second substrate opposite to the absorbent layer using a scriber.

Abstract: A multi-layered capacitor includes a capacitor element in which a plurality of dielectric layers are multi-layered, and which comprises a first inner electrode and a second inner electrode that are alternately formed on neighboring dielectric layers of the plurality of dielectric layers, a first external electrode and a second external electrode which are formed on an outside surface of the capacitor element to be electrically connected to the first inner electrode and the second inner electrode, respectively, and a deformation suppressing electrode which is formed on the outside surface of the capacitor element and separated from the first external electrode and the second external electrode to be electrically isolated from the first inner electrode and the second inner electrode.

Abstract: An array substrate for a multi-vision liquid crystal display device includes a display region; and first to fourth non-display regions surrounding the display region, wherein the first and second non-display regions are opposite to each other and each include a data pad portion connected to a data line, and the third and fourth non-display regions are opposite to each other and each include a gate pad portion connected to a gate line, and wherein the display region is divided into two or four active regions with a seam region between the adjacent active regions, and the seam region has a first width.

Abstract: A multilayer ceramic electronic component having high reliability by reducing equivalent series resistance (ESR) dispersion is provided. Connectivity between internal electrodes and external electrodes is secured by introducing dummy electrodes connected to first and second terminal electrodes, to third and fourth internal electrode layers. ESR dispersion of the multilayer ceramic electronic component is reduced to obtain high reliability.

Abstract: A liquid crystal display device includes first and second substrates, a liquid crystal layer disposed therebetween, first and second gate lines on the first substrate, first, second and third data lines crossing the first and second gate lines to define first, second, third, fourth, fifth and sixth pixel regions, a first pixel electrode and a first common electrode in each of the first, second and third pixel regions, the first pixel electrode connected to a thin film transistor and the first common electrode spaced apart from the first pixel electrode, a second pixel electrode in each of the fourth, fifth and sixth pixel regions, the second pixel electrode connected to the thin film transistor and having a plate shape, a color filter layer including a red color filter corresponding to each of the first and fourth pixel regions, a green color filter corresponding to each of the second and fifth pixel regions, a blue color filter corresponding to each of the third and sixth pixel regions, a second common elect

Abstract: Disclosed herein is a mounting structure of a circuit board having a multi-layered ceramic capacitor thereon, the multi-layered ceramic capacitor including dielectric sheets laminated thereon and external terminal electrodes formed at both ends thereof, the dielectric sheets having internal electrodes formed thereon, and the external terminal electrodes being connected in parallel with the internal electrode, wherein the internal electrodes are disposed to be in parallel with the circuit board, the external terminal electrodes are bonded to lands of the circuit board by a conductive material, and a bonding height (Ts) of the conductive material is lower than a sum of a gap (Ta) between the circuit board and a bottom surface of the multi-layered ceramic capacitor and a thickness (Tc) of a cover layer on a lower portion of the multi-layered ceramic capacitor, whereby vibration noise can be greatly reduced.

Abstract: There is provided a multi-layered ceramic capacitor with reduced internal resistance by forming internal electrode groups including internal electrodes having different lengths.

Abstract: There is provided a multilayer ceramic capacitor, including: a multilayer body in which a plurality of dielectric layers are stacked in a thickness direction; and inner electrode layers formed within the multilayer body and including first and second inner electrodes disposed to be opposed to each other; wherein a ratio (MA1/CA1) of MA1 to CA1 is between 0.07 and 0.20, wherein CA1 represents an area of the multilayer body in a cross section of the multilayer body taken in a length and thickness direction, and MA1 represents an area of a first margin part in the cross section of the multilayer body taken in the length and thickness direction, the first margin part being a portion of the multilayer body, other than a first capacitance forming part thereof in which the first and second inner electrodes overlap in the thickness direction.

Abstract: There is provided a multilayer ceramic capacitor, including: a multilayer body in which a plurality of dielectric layers are stacked in a thickness direction; and inner electrode layers formed within the multilayer body and including first and second inner electrodes disposed to be opposed to each other; wherein a ratio (MA1/CA1) of MA1 to CA1 is between 0.07 and 0.20, wherein CA1 represents an area of the multilayer body in a cross section of the multilayer body taken in a length and thickness direction, and MA1 represents an area of a first margin part in the cross section of the multilayer body taken in the length and thickness direction, the first margin part being a portion of the multilayer body, other than a first capacitance forming part thereof in which the first and second inner electrodes overlap in the thickness direction.

Abstract: Disclosed herein is a mounting structure of a circuit board having a multi-layered ceramic capacitor thereon. The mounting structure of a circuit board having a multi-layered ceramic capacitor thereon, in which a dielectric layer on which inner electrodes are disposed is stacked and external electrode terminals connecting the inner electrodes in parallel are disposed on both ends thereof, wherein the inner electrodes of the multi-layered ceramic capacitor and the circuit board are disposed so as to be a horizontal direction to connect the external electrode terminals with a land on the circuit board by a conductive material and a ratio of a bonding area ASOLEDER of the conductive material to the area AMLCC of the external electrode terminals AMLCC is set to be less than 1.4, thereby remarkably reducing the vibration noise.

Abstract: A multilayer chip capacitor includes a capacitor body including a first capacitor part and a second capacitor part, first and second external electrodes respectively formed on first and second longer side faces of the capacitor body, and third and fourth external electrodes respectively formed on first and second shorter side faces of the capacitor body. The first capacitor part includes first and second internal electrodes of opposite polarity, and the second capacitor part includes third and fourth internal electrodes of opposite polarity. The first to fourth internal electrodes each have one lead. The first to fourth external electrodes are respectively connected to the leads of the first to fourth internal electrodes. A series resonance frequency of the first capacitor part is different from that of the second capacitor part. Equivalent series resistance (ESR1) of the first capacitor part and the equivalent series resistance (ESR2) of the second capacitor part satisfy ERS1?20 m? and 0.7(ESR1)?ESR2?1.

Abstract: A multi-layered capacitor includes a capacitor element in which a plurality of dielectric layers are multi-layered, and which comprises a first inner electrode and a second inner electrode that are alternately formed on neighboring dielectric layers of the plurality of dielectric layers, a first external electrode and a second external electrode which are formed on an outside surface of the capacitor element to be electrically connected to the first inner electrode and the second inner electrode, respectively, and a deformation suppressing electrode which is formed on the outside surface of the capacitor element and separated from the first external electrode and the second external electrode to be electrically isolated from the first inner electrode and the second inner electrode.

Abstract: A packing unit for a plurality of multi-layered ceramic capacitors including: a plurality of multi-layered ceramic capacitors having a thickness TMLCC equal or similar to a width WMLCC; and a packing sheet including a plurality of storing spaces, the capacitors being stored in the storing spaces and internal electrodes of each capacitor being substantially parallel with a bottom of the storing space. A related method includes: transferring a plurality of multi-layered ceramic capacitors having a thickness TMLCC equal or similar to a width WMLCC through a transferring unit; supplying magnetic field to a side of the capacitor so that the internal electrodes of the capacitor are substantially parallel with a bottom of the transferring unit; and storing the multi-layered ceramic capacitor in a storing space of a packing sheet so that the internal electrodes of the capacitor are substantially parallel with a bottom of the storing space.

Abstract: A method of fabricating an LCD device is discussed. The method according to an embodiment includes combining a first substrate having thin film transistors with a second substrate having black matrices and color filters using a sealant. Also, the method includes: forming an absorbent layer which is positioned to overlap with an edge of the sealant and burned by a laser; curing the sealant partially covered with the absorbent layer by irradiating UV light; burning the absorbent layer using a laser beam; and cutting the sealant through the burnt absorbent layer and the second substrate opposite to the absorbent layer using a scriber.

Abstract: A LCD device includes a plurality of color display pixels and a viewing angle control pixel on a first substrate; a backlight shielding pattern formed at a circumferential region of the viewing angle control pixel; a first pixel electrode and a second pixel electrode connected to a drain electrode of a TFT; a protective film formed on a gate line, a data line, the TFT, the first electrode and the second pixel electrode, wherein a first contact hole is formed to expose part of the backlight shielding pattern; a first common electrode connected to the backlight shielding pattern through the first contact hole of the protective film, which is formed to be overlapped with at least part of the first pixel electrode, part of the TFT, and part of the backlight shielding pattern, wherein a plurality of slits overlapped with the first pixel electrode are formed; and a second common electrode formed by corresponding to the first pixel electrode on a second substrate.

Abstract: A multilayer chip capacitor includes a capacitor body including a stack of a plurality of dielectric layers and having first and second side faces and first and second end faces, a plurality of external electrodes of opposite polarity alternated on each of the first and second side faces, and a plurality of internal electrodes each including one or two leads extending to an outer face of the capacitor body and respectively connected to the external electrodes. A horizontal distance between leads of the internal electrodes of opposite polarity adjacent to each other in a stack direction is longer than a pitch between the external electrodes of opposite polarity adjacent to each other on the same side face of the capacitor body.

Abstract: There is provided a multilayer chip capacitor a multilayer chip capacitor including: a capacitor body including first and second capacitor units arranged therein; and first to fourth outer electrodes, wherein the first capacitor unit includes first and second inner electrodes, and the first capacitor unit includes a plurality of capacitor elements each having a pair of the first and second inner electrodes repeatedly laminated, the second capacitor unit includes third and fourth inner electrodes, and the second capacitor unit includes at least one capacitor element having a pair of the third and fourth inner electrodes repeatedly laminated, and at least one of the capacitor elements of the first capacitor unit is different from the other capacitor elements of the first capacitor unit in a lamination number of the first and second inner electrodes or a resonant frequency.

Abstract: The present invention provides a method of mounting a circuit board having thereon a multi-layered ceramic capacitor and a land pattern of a circuit board for the same. The method of mounting a circuit board having thereon a multi-layered ceramic capacitor on which a plurality of dielectric sheet having internal electrodes formed thereon are stacked and the external terminal electrodes connected to the internal electrodes in parallel are formed on both ends thereof includes conductively connecting lands of a circuit board to the external terminal electrodes in such a way that internal electrode layers of the multi-layered ceramic capacitor and the circuit board are arranged in a horizontal direction, wherein a height TS of conductive material to conductively connect the external terminal electrodes to the lands is less than ? of a thickness TMLCC of the multi-layered ceramic capacitor.

Abstract: A multilayer chip capacitor includes a capacitor body including first and second longer side surfaces facing each other and first and second shorter side surfaces facing each other, first and second external electrodes respectively disposed at the first and second longer side surfaces, one or more first internal electrode pairs each including first and second internal electrodes, and one or more second internal electrode pairs each including third and fourth internal electrodes. The first to fourth internal electrodes each have one lead and are sequentially disposed in a stacked direction. The first to fourth internal electrodes have first to fourth leads respectively extending to first to fourth corners or portions adjacent thereto, and alternately connected with the first and second external electrodes. The first internal electrode pair and the second internal electrode pair cause a current to diagonally flow in opposite directions with respect to a long side direction.