Abstract: There is provided a multilayer chip capacitor a multilayer chip capacitor including: a capacitor body including first and second capacitor units arranged therein; and first to fourth outer electrodes, wherein the first capacitor unit includes first and second inner electrodes, and the first capacitor unit includes a plurality of capacitor elements each having a pair of the first and second inner electrodes repeatedly laminated, the second capacitor unit includes third and fourth inner electrodes, and the second capacitor unit includes at least one capacitor element having a pair of the third and fourth inner electrodes repeatedly laminated, and at least one of the capacitor elements of the first capacitor unit is different from the other capacitor elements of the first capacitor unit in a lamination number of the first and second inner electrodes or a resonant frequency.

Abstract: The present invention provides a method of mounting a circuit board having thereon a multi-layered ceramic capacitor and a land pattern of a circuit board for the same. The method of mounting a circuit board having thereon a multi-layered ceramic capacitor on which a plurality of dielectric sheet having internal electrodes formed thereon are stacked and the external terminal electrodes connected to the internal electrodes in parallel are formed on both ends thereof includes conductively connecting lands of a circuit board to the external terminal electrodes in such a way that internal electrode layers of the multi-layered ceramic capacitor and the circuit board are arranged in a horizontal direction, wherein a height TS of conductive material to conductively connect the external terminal electrodes to the lands is less than ? of a thickness TMLCC of the multi-layered ceramic capacitor.

Abstract: A multilayer chip capacitor includes a capacitor body including first and second longer side surfaces facing each other and first and second shorter side surfaces facing each other, first and second external electrodes respectively disposed at the first and second longer side surfaces, one or more first internal electrode pairs each including first and second internal electrodes, and one or more second internal electrode pairs each including third and fourth internal electrodes. The first to fourth internal electrodes each have one lead and are sequentially disposed in a stacked direction. The first to fourth internal electrodes have first to fourth leads respectively extending to first to fourth corners or portions adjacent thereto, and alternately connected with the first and second external electrodes. The first internal electrode pair and the second internal electrode pair cause a current to diagonally flow in opposite directions with respect to a long side direction.

Abstract: An array substrate for a liquid crystal display device including a substrate having a display region and a non-display region at one side of the display region; gate lines along a first direction and in the display region; data lines along a second direction and in the display region, the data lines crossing the gate lines to define pixel regions; auxiliary gate lines along the second direction and in the display region, the auxiliary gate lines respectively connected to the gate lines; data pad electrodes in the non-display region and electrically connected to the data lines, respectively; and gate pad electrodes in the non-display region and electrically connected to the auxiliary gate lines, respectively.

Abstract: An array substrate for a multi-vision liquid crystal display device includes a display region; and first to fourth non-display regions surrounding the display region, wherein the first and second non-display regions are opposite to each other and each include a data pad portion connected to a data line, and the third and fourth non-display regions are opposite to each other and each include a gate pad portion connected to a gate line, and wherein the display region is divided into two or four active regions with a seam region between the adjacent active regions, and the seam region has a first width.

Abstract: There is provided a multilayer capacitor including: a capacitor body where a plurality of dielectric layers are laminated, the capacitor body including first and second surfaces opposing each other in a laminated direction, wherein the first surface provides a mounting surface; a plurality of first and second inner electrodes; an inner connecting conductor; and a plurality of first and second outer electrodes formed on an outer surface of the body, wherein a corresponding one of the outer electrodes having identical polarity to the inner connecting conductor includes at least one outer terminal formed on the first surface of the body to connect to the inner connecting conductor, and at least one outer connecting conductor formed on the second surface of the body to connect a corresponding one of the inner electrodes of identical polarity to the inner connecting conductor.

Abstract: Provided is an electrode pad for mounting an electronic component on a surface of a circuit board. The electrode pad includes first and second electrode parts facing each other, and third and fourth electrode parts facing each other. The third and fourth electrode parts are disposed adjacent to the first and second electrode parts for forming corners of the electrode pad together with the first and second electrode parts. At least one of the first to fourth electrode parts includes a chamfered surface formed by cutting a corner of the at least one of the first to fourth electrode parts forming the corner of the electrode pad. Therefore, when the electrode pad is used for mounting an electronic component, the width of an outer electrode of the electronic component can be sufficiently increased, and thus the shape or size of the outer electrode can be easily adjusted.

Abstract: Disclosed herein are a coupling structure for a multi-layered chip filter capable of overcoming a limitation of an existing coupling by improving a coupling structure and a multi-layered chip filter with the structure. The coupling structure according to an exemplary embodiment of the present invention includes: at least two overlap portion patterns each overlapped with a pattern formed on a resonator layer stacked therewith to form at least two overlap areas spaced from each other; and a connecting portion pattern formed by connecting at least three linear lines having a predetermined length to each other to connect the at least two overlap portion patterns to each other.

Abstract: There is provided a multilayer chip capacitor including: a capacitor body including first and second capacitor units arranged in a laminated direction; and first to fourth outer electrodes formed on side surfaces of the capacitor body, respectively, wherein the first capacitor unit includes first and second inner electrodes of different polarities alternately arranged in the capacitor body to oppose each other while interposing a corresponding one of dielectric layers, the second capacitor unit includes third and fourth inner electrodes of different polarities alternately arranged in the capacitor body to oppose each other while interposing another corresponding one of the dielectric layers, the first and second capacitor units are electrically insulated from each other, and the first capacitor unit operates in a first frequency range and the second capacitor unit operates in a second frequency range lower than the first frequency range.

Abstract: A circuit board device includes a circuit board comprising a mounting area, and first and second power lines and a ground pad formed on the mounting area, and a vertical multilayer chip capacitor (MLCC) comprising a capacitor body, a plurality of first and second polarity inner electrodes, first and second outer electrodes, and a third outer electrode, wherein the first and second power lines are separately disposed on the mounting area, connected to the first and second outer electrodes, and electrically connected to each other only by the vertical MLCC, and the ground pad is disposed between the first and second power lines and connected to the third outer electrode.

Abstract: Disclosed is a method of implementing controlled equivalent series resistance (ESR) having low equivalent series inductance (ESL) of a multi-layer chip capacitor which includes a plurality of internal electrodes each having first polarity or second polarity which is opposite to the first polarity, and dielectric layers each disposed between the internal electrodes of the first polarity and the second polarity, wherein the internal electrodes having the first polarity and the internal electrodes having the second polarity are alternated at least once to form one or more blocks being stacked.

Abstract: There is provided a multi-layered ceramic capacitor with reduced internal resistance by forming internal electrode groups including internal electrodes having different lengths.

Abstract: A multilayer filter includes: a ceramic body in which a plurality of dielectric layers are laminated; an external ground electrode provided on an outer surface of the ceramic body and connected to a ground; an inductor pattern electrode provided on at least one of the dielectric layers and having one end connected to the external ground electrode; a capacitor pattern electrode provided on at least one of the dielectric layers; an external terminal electrode electrically connecting the inductor pattern electrode to the capacitor pattern electrode and forming a closed loop for generating inductance through the external ground electrode; and a variable dielectric layer provided between the capacitor pattern electrode and the inductor pattern electrode and adjusting a magnitude of inductance generated by the inductor pattern electrode.

Abstract: A multilayer chip capacitor includes a capacitor body provided by a stack of a plurality of dielectric layers, a plurality of internal electrodes disposed in the capacitor body such that the internal electrodes of opposite polarities are alternately disposed to face each other with the dielectric layer interposed between each facing set of the internal electrodes, and a plurality of external electrodes disposed on an outer face of the capacitor body and electrically connected with the internal electrode. Each of the plurality of internal electrodes includes a main electrode part, and at least one lead extending from the main electrode part to a side face of the capacitor body and connected to a corresponding one of the external electrodes. The lead extends to the corresponding external electrode to be inclined with respect to the main electrode part thereof.

Abstract: There are provided a multilayer chip capacitor and a circuit board device. The multilayer chip capacitor includes a capacitor body including a plurality of dielectric layers that are stacked, first and second outer electrodes formed on an outer surface of the capacitor body and having opposite polarity, first and second inner electrodes opposing each other, interleaved with the dielectric layers in the capacitor body, and each including an electrode plate forming capacitance and a lead extending from the electrode plate, the lead of the first inner electrode and the lead of the second electrode being respectively connected to the first and second outer electrodes, and third inner electrodes interposed between the first and second inner electrodes. At least one of the third inner electrodes adjacent to the first inner electrode includes a conductive pattern having the same shape as the lead of the first inner electrode and is connected to the first outer electrode.

Abstract: A multilayer chip capacitor including: a capacitor body having a lamination structure where a plurality of dielectric layers are laminated and including a first capacitor part and a second capacitor part arranged according to a lamination direction; first to fourth outer electrodes formed on side surfaces of the capacitor body, the first and third outer electrodes having the same polarity and the second and fourth outer electrodes having the same polarity opposite to that of the first outer electrode; and one or more connection conductor lines formed on an outer surface of the capacitor body and connecting the first outer electrode to the third outer electrode or connecting the second outer electrode to the fourth outer electrode.

Abstract: The present invention is related to a method for transferring substrates. The method comprise simultaneously transferring two substrates, by means of a transfer unit, between first support plates disposed to be vertically spaced apart from each other and second support plates arranged abreast in a lateral direction. The transfer unit comprises a top blade and a bottom blade converted to a folded state where they are vertically disposed to face each other and an unfolded state where they rotate at a preset angle in opposite directions. The transfer unit place/take a substrate on/out of the first support plates under the folded state and place/take a substrate on/out of the second support plates under the unfolded state.

Abstract: A multilayer chip capacitor includes: a capacitor body having first and second side surfaces and a bottom surface; a plurality of first and second internal electrodes in the capacitor body; first and second external electrodes having a first polarity and formed on the first and second side surfaces, respectively, to cover a respective lower edge of the side surfaces and to partially extend to the bottom surface; and a third external electrode having a second polarity and formed on the bottom surface. The internal electrodes are disposed in perpendicular to the bottom surface. Each of the first internal electrodes has a first lead drawn to the first side and bottom surfaces and a second lead drawn to the second side and bottom surfaces. Each of the second internal electrodes has a third lead drawn to the bottom surface.

Abstract: A multilayer capacitor array having a plurality of multilayer capacitor devices formed in a single multilayer structure, the multilayer capacitor array including: a capacitor body formed by depositing a plurality of dielectric layers and having first and second side surfaces opposite to each other; a plurality of first polarity internal electrodes and second polarity internal electrodes, disposed oppositely to each other in the capacitor body, interposing the dielectric layer there between, and formed of a single electrode plate comprising a single lead, respectively; and a plurality of first polarity external electrodes and second polarity external electrodes, formed on the first side surface and second side surface, respectively, and connected to a correspondent polarity internal electrode via the lead, the first polarity external electrode formed on the first side surface and the second polarity external electrode formed on the second side surface, wherein the numbers of the first polarity external electro

Abstract: A multilayer chip capacitor including: a capacitor body formed of a lamination of a plurality of dielectric layers and having a bottom surface that is a mounting area; a plurality of internal electrodes disposed to be opposite to each other, interposing a dielectric layer there between in the capacitor body and having one lead extended to the bottom surface, respectively; and three or more external electrodes formed on the bottom surface and connected to corresponding internal electrodes via the leads, wherein the internal electrodes are vertically disposed on the bottom surface, and the leads of the internal electrodes having a different polarity from each other, adjacent to each other in a lamination direction, are disposed to be always adjacent to each other in a horizontal direction.