Patents by Inventor Dong Sik Lee
Dong Sik Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10868038Abstract: A memory device may include multiple channel regions extending in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate to be adjacent at least a portion of the plurality of channel regions, an interlayer insulating layer disposed on the plurality of gate electrode layers, a plurality of cell contact plugs passing through the interlayer insulating layer. Each of the plurality of cell contacts is connected to each of the plurality of gate electrode layers. A vertical insulating layer extends from the interlayer insulating layer disposed between the plurality of channel regions and the plurality of cell contact plugs and has a portion surrounded by at least one of the plurality of gate electrode layers.Type: GrantFiled: July 9, 2019Date of Patent: December 15, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seok Cheon Baek, Young Woo Kim, Dong Sik Lee, Min Yong Lee, Woong Seop Lee
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Publication number: 20200373324Abstract: A semiconductor device is provided. The semiconductor device includes a stack structure that includes a plurality of dielectric layers spaced apart from each other on a substrate, a plurality of electrodes interposed between the plurality of dielectric layers, and a plurality of stopper layers interposed between the plurality of dielectric layers; and a vertical channel structure that penetrates the stack structure. Each of the plurality of electrodes and the plurality of stopper layers is disposed in a corresponding empty space interposed between the plurality of dielectric layers, the plurality of stopper layers includes a first stopper layer and a second stopper layer that is interposed between the first stopper layer and the substrate, and at least one of the plurality of electrodes is interposed between the first stopper layer and the second stopper layer.Type: ApplicationFiled: January 27, 2020Publication date: November 26, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: BYUNGJIN LEE, Dong-sik Lee, Joon-Sung Lim
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Publication number: 20200357817Abstract: Provided is a three-dimensional semiconductor memory device include a first stack structure and a second stack structure adjacent to each other on a substrate, a first common source plug between the first stack structure and the second stack structure, a second common source plug between the first stack structure and the second stack structure, and a vertical dielectric structure between the first common source plug and the second common source plug. Each of the first stack structure and the second stack structure may include a plurality of insulation layers and a plurality of electrodes alternately stacked on the substrate. The first common source plug may be connected to the substrate. The second common source plug may be spaced apart from the substrate.Type: ApplicationFiled: June 1, 2020Publication date: November 12, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Kangyoon CHOI, Gilsung LEE, Dong-Sik LEE, Yongsik YIM, Eunsuk CHO
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Patent number: 10818678Abstract: A three-dimensional semiconductor memory device includes a substrate including a peripheral circuit region and a cell array region, a plurality of peripheral gate stacks disposed in the peripheral circuit region, and an electrode structure disposed in the cell array region. The electrode structure includes a lower electrode, a lower insulating layer disposed on the lower electrode, and upper electrodes and upper insulating layers alternately stacked on the lower insulating layer. The lower insulating layer extends from the cell array region into the peripheral circuit region and covers the peripheral gate stacks. The lower insulating layer includes a first lower insulating layer and a second lower insulating layer sequentially stacked on one another. The first lower insulating layer includes a first insulating material, and the second lower insulating layer includes a second insulating material different from the first insulating material.Type: GrantFiled: April 16, 2018Date of Patent: October 27, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Min Hwang, Dong-Sik Lee, Joon-Sung Lim
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Publication number: 20200227435Abstract: A semiconductor device includes gate electrodes spaced apart from each other in a first direction perpendicular to a substrate's upper surface, and extending by different lengths in a second direction perpendicular to the first direction. The device further includes first and second channels penetrating the gate electrodes and extending in the first direction, a horizontal portion disposed in lower portions of the gate electrodes and connecting lower portions of the first and second channels to each other, and a source line disposed in an upper portion of the second channel and connected to the second channel. The gate electrodes include memory cell electrodes included in memory cells, a first ground select electrode disposed in lower portions of the memory cell electrodes, a second ground select electrode disposed in upper portions of the memory cell electrodes, and a string select electrode disposed in upper portions of the memory cell electrodes.Type: ApplicationFiled: November 18, 2019Publication date: July 16, 2020Inventors: Sung Min Hwang, Joon Sung Lim, Woo Sung Yang, Dong Sik Lee
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Publication number: 20200212061Abstract: A three-dimensional (3D) semiconductor memory device includes a substrate that includes a cell array region and a connection region, a dummy trench formed on the connection region, an electrode structure on the substrate and that includes vertically stacked electrodes that have a staircase structure on the connection region, a dummy insulating structure disposed in the dummy trench, the dummy insulating structure including an etch stop pattern spaced apart from the substrate and the electrode structure, a cell channel structure disposed on the cell array region and that penetrates the electrode structure and makes contact with the substrate, and a dummy channel structure disposed on the connection region and that penetrates the electrode structure and a portion of the dummy insulating structure and that makes contact with the etch stop pattern.Type: ApplicationFiled: October 24, 2019Publication date: July 2, 2020Inventors: KANGYOON CHOI, DONG-SIK LEE, JONGWON KIM, GILSUNG LEE, EUNGSUK CHO, BYUNGYONG CHOI, SUNG-MIN HWANG
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Patent number: 10700085Abstract: A vertical memory device is provided. The vertical memory device includes a substrate, first gate electrodes, a channel, first wirings, and second wirings. The substrate includes a cell region and a peripheral circuit region. The first gate electrodes are spaced apart from each other in a first direction on the cell region of the substrate, the first direction being substantially perpendicular to the substrate. The channel extends through a portion of the first gate electrodes in the first direction on the cell region. The first wirings are formed on the cell region, and are disposed at first levels that are higher in the first direction than gate electrode levels on which the first gate electrodes are respectively formed. The second wirings are formed on the peripheral circuit region, and are disposed at the first levels and at a second level that is higher than the gate electrode levels.Type: GrantFiled: June 18, 2018Date of Patent: June 30, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Min Hwang, Dong-Sik Lee, Joon-Sung Lim
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Publication number: 20200194457Abstract: In a 3D semiconductor memory device, a stack structure includes electrodes and first insulating layers disposed between the electrodes. The stack structure has a stair structure on a connection region. A vertical channel structure penetrates the stack structure on a cell array region. A vertical dummy structure penates the stair structure on the connection region. A second insulating layer is selectively disposed on the cell array region. A maximum thickness of the second insulating layer ranges from 1.5 times to 10 times a maximum thickness of the first insulating layer on the second insulating layer. The vertical channel structure includes an abrupt diameter change at a level of a top surface of the second insulating layer. The abrupt diameter change has a surface which is parallel to the top surface of the second insulating layer and is substantially coplanar with the top surface of the second insulating layer.Type: ApplicationFiled: September 17, 2019Publication date: June 18, 2020Inventors: Kang-Won Lee, Jaeyoung Song, Dong-Sik Lee, Donghoon Jang
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Patent number: 10672792Abstract: Provided is a three-dimensional semiconductor memory device include a first stack structure and a second stack structure adjacent to each other on a substrate, a first common source plug between the first stack structure and the second stack structure, a second common source plug between the first stack structure and the second stack structure, and a vertical dielectric structure between the first common source plug and the second common source plug. Each of the first stack structure and the second stack structure may include a plurality of insulation layers and a plurality of electrodes alternately stacked on the substrate. The first common source plug may be connected to the substrate. The second common source plug may be spaced apart from the substrate.Type: GrantFiled: February 4, 2019Date of Patent: June 2, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Kangyoon Choi, Gilsung Lee, Dong-Sik Lee, Yongsik Yim, Eunsuk Cho
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Publication number: 20190371808Abstract: Provided is a three-dimensional semiconductor memory device include a first stack structure and a second stack structure adjacent to each other on a substrate, a first common source plug between the first stack structure and the second stack structure, a second common source plug between the first stack structure and the second stack structure, and a vertical dielectric structure between the first common source plug and the second common source plug. Each of the first stack structure and the second stack structure may include a plurality of insulation layers and a plurality of electrodes alternately stacked on the substrate. The first common source plug may be connected to the substrate. The second common source plug may be spaced apart from the substrate.Type: ApplicationFiled: February 4, 2019Publication date: December 5, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Kangyoon Choi, Gilsung Lee, Dong-Sik Lee, Yongsik Yim, Eunsuk Cho
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Publication number: 20190333935Abstract: A memory device may include multiple channel regions extending in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate to be adjacent at least a portion of the plurality of channel regions, an interlayer insulating layer disposed on the plurality of gate electrode layers, a plurality of cell contact plugs passing through the interlayer insulating layer. Each of the plurality of cell contacts is connected to each of the plurality of gate electrode layers. A vertical insulating layer extends from the interlayer insulating layer disposed between the plurality of channel regions and the plurality of cell contact plugs and has a portion surrounded by at least one of the plurality of gate electrode layers.Type: ApplicationFiled: July 9, 2019Publication date: October 31, 2019Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seok Cheon BAEK, Young Woo Kim, Dong Sik Lee, Min Yong Lee, Woong Seop Lee
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Patent number: 10373975Abstract: A memory device may include multiple channel regions extending in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate to be adjacent at least a portion of the plurality of channel regions, an interlayer insulating layer disposed on the plurality of gate electrode layers, a plurality of cell contact plugs passing through the interlayer insulating layer. Each of the plurality of cell contacts is connected to each of the plurality of gate electrode layers. A vertical insulating layer extends from the interlayer insulating layer disposed between the plurality of channel regions and the plurality of cell contact plugs and has a portion surrounded by at least one of the plurality of gate electrode layers.Type: GrantFiled: October 17, 2018Date of Patent: August 6, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seok Cheon Baek, Young Woo Kim, Dong Sik Lee, Min Yong Lee, Woong Seop Lee
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Publication number: 20190051664Abstract: A memory device may include multiple channel regions extending in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate to be adjacent at least a portion of the plurality of channel regions, an interlayer insulating layer disposed on the plurality of gate electrode layers, a plurality of cell contact plugs passing through the interlayer insulating layer. Each of the plurality of cell contacts is connected to each of the plurality of gate electrode layers. A vertical insulating layer extends from the interlayer insulating layer disposed between the plurality of channel regions and the plurality of cell contact plugs and has a portion surrounded by at least one of the plurality of gate electrode layers.Type: ApplicationFiled: October 17, 2018Publication date: February 14, 2019Inventors: SEOK CHEON BAEK, YOUNG WOO KIM, DONG SIK LEE, MIN YONG LEE, WOONG SEOP LEE
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Publication number: 20190035798Abstract: A three-dimensional semiconductor memory device includes a substrate including a peripheral circuit region and a cell array region, a plurality of peripheral gate stacks disposed in the peripheral circuit region, and an electrode structure disposed in the cell array region. The electrode structure includes a lower electrode, a lower insulating layer disposed on the lower electrode, and upper electrodes and upper insulating layers alternately stacked on the lower insulating layer. The lower insulating layer extends from the cell array region into the peripheral circuit region and covers the peripheral gate stacks. The lower insulating layer includes a first lower insulating layer and a second lower insulating layer sequentially stacked on one another. The first lower insulating layer includes a first insulating material, and the second lower insulating layer includes a second insulating material different from the first insulating material.Type: ApplicationFiled: April 16, 2018Publication date: January 31, 2019Inventors: SUNG-MIN HWANG, DONG-SIK LEE, JOON-SUNG LIM
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Publication number: 20190035808Abstract: A vertical memory device is provided. The vertical memory device includes a substrate, first gate electrodes, a channel, first wirings, and second wirings. The substrate includes a cell region and a peripheral circuit region. The first gate electrodes are spaced apart from each other in a first direction on the cell region of the substrate, the first direction being substantially perpendicular to the substrate. The channel extends through a portion of the first gate electrodes in the first direction on the cell region. The first wirings are formed on the cell region, and are disposed at first levels that are higher in the first direction than gate electrode levels on which the first gate electrodes are respectively formed. The second wirings are formed on the peripheral circuit region, and are disposed at the first levels and at a second level that is higher than the gate electrode levels.Type: ApplicationFiled: June 18, 2018Publication date: January 31, 2019Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Min HWANG, Dong-Sik LEE, Joon-Sung LIM
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Patent number: 10128263Abstract: A memory device may include multiple channel regions extending in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate to be adjacent at least a portion of the plurality of channel regions, an interlayer insulating layer disposed on the plurality of gate electrode layers, a plurality of cell contact plugs passing through the interlayer insulating layer. Each of the plurality of cell contacts is connected to each of the plurality of gate electrode layers. A vertical insulating layer extends from the interlayer insulating layer disposed between the plurality of channel regions and the plurality of cell contact plugs and has a portion surrounded by at least one of the plurality of gate electrode layers.Type: GrantFiled: July 29, 2016Date of Patent: November 13, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Seok Cheon Baek, Young Woo Kim, Dong Sik Lee, Min Yong Lee, Woong Seop Lee
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Patent number: 10128266Abstract: A semiconductor device includes lower and upper selection lines, a cell gate structure, a lower dummy structure and an upper dummy structure. The cell gate structure is between the lower and upper selection lines and includes cell gate electrodes stacked in a first direction. The lower dummy structure is between the lower selection line and the cell gate structure and includes a lower dummy gate line spaced from a lowermost one of the cell gate electrodes by a first distance. The upper dummy structure is between the upper selection line and the cell gate structure and includes an upper dummy gate line spaced from an uppermost one of the cell gate electrodes by a second distance. The cell gate electrodes are spaced by a third distance less than each of the first and second distances.Type: GrantFiled: May 10, 2017Date of Patent: November 13, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung Hoon Lee, Keejeong Rho, Sejun Park, Jinhyun Shin, Dong-Sik Lee, Woong-Seop Lee
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Patent number: 9911745Abstract: A vertically integrated circuit device can include a substrate having a first region reserved for first functional circuits of the vertically integrated circuit device, where the first functional circuits has a substantially constant top surface level across the first region and having a second region reserved for second functional circuits of the vertically integrated circuit device and spaced apart from the first region. The second functional circuits can have a varied top surface level across the second region. A doped oxidation suppressing material can be included in the substrate and can extend from the first region to the second region at an interface of the substrate with the first functional circuits and the second functional circuits, respectively.Type: GrantFiled: February 7, 2017Date of Patent: March 6, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Sik Lee, Youngwoo Kim, Jinhyun Shin, Jung Hoon Lee
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Publication number: 20170243886Abstract: A semiconductor device includes lower and upper selection lines, a cell gate structure, a lower dummy structure and an upper dummy structure. The cell gate structure is between the lower and upper selection lines and includes cell gate electrodes stacked in a first direction. The lower dummy structure is between the lower selection line and the cell gate structure and includes a lower dummy gate line spaced from a lowermost one of the cell gate electrodes by a first distance. The upper dummy structure is between the upper selection line and the cell gate structure and includes an upper dummy gate line spaced from an uppermost one of the cell gate electrodes by a second distance. The cell gate electrodes are spaced by a third distance less than each of the first and second distances.Type: ApplicationFiled: May 10, 2017Publication date: August 24, 2017Inventors: Jung Hoon LEE, Keejeong RHO, Sejun PARK, Jinhyun SHIN, Dong-Sik LEE, Woong-Seop LEE
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Patent number: 9711531Abstract: A method of fabricating a semiconductor device can include forming a channel hole in a vertical stack of alternating insulating and sacrificial layers to form a recess in a substrate. A selectively epitaxial growth can be performed to provide a lower semiconductor pattern in the recess using material of the substrate as a seed and a recess can be formed to penetrate an upper surface of the lower semiconductor pattern via the channel hole.Type: GrantFiled: October 5, 2016Date of Patent: July 18, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Woong-Seop Lee, Jongyoon Choi, Jinhyun Shin, Dong-Sik Lee