Abstract: Provided is an apparatus and method for collaborative location awareness based on weighted maximum likelihood estimation (MLE), which is configured to improve accuracy of location awareness between nodes in estimating a location of a blind node. The method includes exchanging location awareness information with a reference node and a location-estimated blind node among peripheral nodes when location awareness is requested, performing location estimation based on weighted MLE, performing location calculation by using the location awareness information and an estimate obtained through the location estimation, and providing location awareness results of blind nodes.

Abstract: A functional paint composition prevents a power loss caused by corrosion of a structure with high voltage electric current. The paint composition includes, by weight, an acrylic urethane resin of 100 parts as a principal resin, with a potassium silicate resin of 5 to 20 parts, an auxiliary resin of 5 to 10 parts, a functional pigment of 100 to 250 parts, and functional additives of 1 to 2 parts. Accordingly, in embodiments of the disclosure, causes of a negative influence on high voltage electric current not solved in general paint are eliminated, and the economy is considered being applicable to all kinds of materials and composition layers of objects to be coated, thereby providing an effect even in a repair coating for electrical lines and stuck-metal parts having electric current and structures not having an electric current, i.e., steel tower, bridge, storage tanks, steel structures and coating panels, etc.

Abstract: Disclosed herein are a printed circuit board and a fabrication method thereof, which can improve electrical properties, shorten processing time, and reduce the thickness of a chip package by achieving an ultra-thin fine circuit pattern. The printed circuit board includes an insulating material; a via-hole formed in a given location of the insulating material; a copper seed layer formed through ion beam surface treatment and vacuum deposition on the surface of the insulating material having the via-hole formed therein; and a copper pattern plating layer formed on a given region of the insulating material, which has the copper seed layer formed thereon, and in the via-hole.

Abstract: The present invention relates to a method for monitoring error in prescription data employing barcode system comprising the steps of recording a dosage type and dose of a medicament in a prescription order by way of encoding those in a form of barcode, inputting information recorded in the barcode-prescription order, comparing the information with a database information about the prescribed medicament, and displaying the appropriateness of the dosage type and dose of the medicament. In accordance with the method for monitoring error in prescription data employing barcode system of the invention, the error in prescription data including dosage types and doses of prescribed medicaments can be reconsidered, which makes possible its practical application for the treatment of diseases in a more safe manner.

Abstract: A method of manufacturing a build-up printed circuit board, in which the circuit of a build-up printed circuit board including a core layer and an outer layer is realized by forming the metal seed layer of the core layer using a dry process, consisting of ion beam surface treatment and vacuum deposition, instead of a conventional wet process, including a wet surface roughening process and electroless plating. When the wet process is replaced with the dry process in the method of the invention, the circuit layer can be formed in an environmentally friendly manner, and as well, all circuit layers of the substrate including the core layer and the outer layer can be manufactured through a semi-additive process. Further, the peel strength between the resin substrate and the metal layer can be increased, thus realizing a highly reliable fine circuit.

Abstract: According to an embodiment, a method of fabricating a thin film transistor comprises forming a gate electrode on a substrate; forming a gate insulating layer on the gate electrode; forming a semiconductor layer on the gate insulating layer, the semiconductor layer corresponding to the gate electrode; forming first and second barrier patterns on the semiconductor layer, the first and second barrier patterns including copper nitride; and forming source and drain electrodes on the first and second barrier patterns, respectively, the source and drain electrodes including pure copper.

Abstract: There is provided a digital MAC apparatus for an IEEE 802.15.4 based communication system, which is implemented in hardware. The digital MAC apparatus having a processor of a Wireless Personal Area Network (WPAN) communication system and a data bus transferring data includes a frame generating unit generating and outputting a frame on the basis of input data; a frame parsing unit parsing an input frame input through the data bus, and generating and outputting a control signal or transmission and receipt data; and a controller operating at least one of the frame generating unit and the frame parsing unit according to the generated control signal, and communicating the output frame or data with the processor according to the operation.

Abstract: A filter tuning circuit for a wireless communication system is provided. A filter tuning circuit includes a comparator and a counter which control a transconvertance value of a differential transconverter to tune a filter.

Abstract: Disclosed herein is a hybrid channel estimation method and system for an Orthogonal Frequency Division Multiplexing (OFDM) wireless communication system. The hybrid channel estimation method includes the steps of acquiring a first channel coefficient using decision-directed channel estimation; acquiring a second channel coefficient using pilot-symbol-aided channel estimation; and calculating the final channel coefficient of a received signal by multiplying the first and second coefficients by first and second multiplication coefficients, respectively, and adding the multiplication results.

Abstract: A semiconductor device includes a P-channel metal-oxide semiconductor (PMOS) transistor and an N-channel metal-oxide semiconductor (NMOS) transistor formed in three or more fin active regions in a vertical stack structure, an input metal line contacting gates of the PMOS transistor and NMOS transistor, a power supply voltage metal line contacting four channel active regions of the PMOS transistor, a contact metal line contacting two channel active regions of the NMOS transistor, and an output metal line contacting four channel active regions of the PMOS transistor and the NMOS transistor.

Abstract: Provided are a small low power embedded system and a preemption avoidance method thereof. A method for avoiding preemption in a small low power embedded system includes fetching and running a periodic atomic task from a periodic run queue, reducing any one of periodic atomic tasks or performing the change of a task after changing a field of the run periodic atomic task into a run standby state, according to a result value of the run of the periodic atomic task, fetching a sporadic atomic task from a sporadic run queue, and acquiring a system clock, running the fetched sporadic atomic task according to run time in the worst condition, and reducing any one of sporadic atomic tasks or performing the change of an event after a field of the run sporadic atomic task into a run standby state, according to a result value of the run of the sporadic atomic task.

Abstract: The present invention relates to a copper wire in a semiconductor device in which a barrier layer is formed for improving adhesion of a copper wire without any additional fabricating step; a method for fabricating the same, and a flat panel display device with the same. The copper wire includes a barrier layer formed on an underlying structure, and a copper conductive layer on the barrier layer, wherein the barrier layer includes at least one of a Cu2O layer and a CuOxNy layer.

Abstract: Provided is an apparatus and method for collaborative location awareness based on weighted maximum likelihood estimation (MLE), which is configured to improve accuracy of location awareness between nodes in estimating a location of a blind node. The method includes exchanging location awareness information with a reference node and a location-estimated blind node among peripheral nodes when location awareness is requested, performing location estimation based on weighted MLE, performing location calculation by using the location awareness information and an estimate obtained through the location estimation, and providing location awareness results of blind nodes.

Abstract: The present invention relates to a method and apparatus for detecting STBC-OFDM signals in time-variant channels. The method includes a step of demodulating STBC-OFDM modulation signals into OFDM reception symbols using Fast Fourier Transform (FFT); a step of estimating a frequency response for each sub-channel; an STBC decoding step of calculating decision variables determining the A transmit data symbols that are transmitted during the B OFDM symbol periods for each sub-channel; and a step of determining the transmit data symbols based on the decision variables calculated at the STBC decoding step. In this case, the decision variables are calculated using a linear equation that allows a squared Euclidean distance from OFDM reception symbols, which are demodulated during the B symbol periods, to have a local minimum for each decision variable when the STBC encoding and the frequency responses estimated during the B OFDM symbol periods are applied.

Abstract: According to an embodiment, a method of fabricating a thin film transistor comprises forming a gate electrode on a substrate; forming a gate insulating layer on the gate electrode; forming a semiconductor layer on the gate insulating layer, the semiconductor layer corresponding to the gate electrode; forming first and second barrier patterns on the semiconductor layer, the first and second barrier patterns including copper nitride; and forming source and drain electrodes on the first and second barrier patterns, respectively, the source and drain electrodes including pure copper.

Abstract: Disclosed herein is a method for eliminating the reception interference signal of a Space-Time Block Coded Orthogonal Frequency-Division Multiplexing (STBC-OFDM) system in a high-speed mobile channel. The method includes the following steps. At the first step, the gain of a channel combined at a receiving end is estimated in the case of using the STBC-OFDM system on a time-varying channel. At the second step, first temporary decision symbols are obtained by performing comparison on the estimated gain. At the third step, second temporary decision symbols are obtained using the first temporary decision symbols. At the fourth step, self-channel interference (SCI) terms are eliminated using the second temporary decision symbols and third temporary decision symbols are obtained. At the fifth step, final data symbols are obtained using the third temporary decision symbols.

Abstract: Disclosed is a method of manufacturing a build-up printed circuit board, in which the circuit of a build-up printed circuit board including a core layer and an outer layer is realized by forming the metal seed layer of the core layer using a dry process, consisting of ion beam surface treatment and vacuum deposition, instead of a conventional wet process, including a wet surface roughening process and electroless plating. When the wet process is replaced with the dry process in the method of the invention, the circuit layer can be formed in an environmentally friendly manner, and as well, all circuit layers of the substrate including the core layer and the outer layer can be manufactured through a semi-additive process. Further, the peel strength between the resin substrate and the metal layer can be increased, thus realizing a highly reliable fine circuit.

Abstract: A semiconductor device includes a P-channel metal-oxide semiconductor (PMOS) transistor and an N-channel metal-oxide semiconductor (NMOS) transistor formed in three or more fin active regions in a vertical stack structure, an input metal line contacting gates of the PMOS transistor and NMOS transistor, a power supply voltage metal line contacting four channel active regions of the PMOS transistor, a contact metal line contacting two channel active regions of the NMOS transistor, and an output metal line contacting four channel active regions of the PMOS transistor and the NMOS transistor.

Abstract: The disclosed apparatus includes a main control unit (MCU) interface unit for adjusting the timing of data transmission, a register unit for storing control data, a threshold value, an offset value, and an error rate received from the MCU interface unit, and for outputting the stored data and values, a control logic unit for controlling selection of a threshold value, based on the control data stored in the register unit, a reference data selecting unit for selectively outputting, as threshold values, the threshold value and offset value respectively stored in the register unit or an external threshold value and an external offset value, under control of the control logic unit, and a data processing unit for determining, based on threshold values to be selectively outputted by the reference data selecting unit, whether or not the serial data received via a power line is valid data, and for outputting the data.

Abstract: A contact structure for transferring an electrical signal from a main body to a print head, particularly a printing apparatus having a line contact structure, is provided. The printing apparatus comprises an electrical connecting portion formed at an end of the cable; a plurality of contact points formed at the electrical connecting portion, each in a form of a hollow projection so as to correspond to a circuit portion of the print head and having a hole form at an apex of the projection; a fixing portion for fixing the electrical connecting portion to the main body; and an elastic member interposed between the electrical connecting portion and the fixing portion and having a plurality of protruding portions corresponding to the plurality of contact points, wherein the elastic member presses the electrical connecting portion so that the plurality of contact points are in line contact with the circuit portion of the print head when the print head is mounted in the main body.