Abstract: A contact structure for transferring an electrical signal from a main body to a print head, particularly a printing apparatus having a line contact structure, is provided. The printing apparatus comprises an electrical connecting portion formed at an end of the cable; a plurality of contact points formed at the electrical connecting portion, each in a form of a hollow projection so as to correspond to a circuit portion of the print head and having a hole form at an apex of the projection; a fixing portion for fixing the electrical connecting portion to the main body; and an elastic member interposed between the electrical connecting portion and the fixing portion and having a plurality of protruding portions corresponding to the plurality of contact points, wherein the elastic member presses the electrical connecting portion so that the plurality of contact points are in line contact with the circuit portion of the print head when the print head is mounted in the main body.

Abstract: Disclosed are a brightness-enhancing light guiding plate and an LCD using the same, in which a brightness enhancing recess portion for improving an optical distribution, changing a light path and enhancing brightness is formed at a surface by which light is reflected. The brightness enhancing recess portion has a reflection recess surface having a maximum surface area and a non-reflection recess surface having a minimum surface area, thereby improving the brightness, changing the light path and improving the optical distribution and thus improving a displaying performance.

Abstract: Disclosed are a brightness-enhancing light guiding plate and an LCD using the same, in which a brightness enhancing recess portion for improving an optical distribution, changing a light path and enhancing brightness is formed at a surface by which light is reflected. The brightness enhancing recess portion has a reflection recess surface having a maximum surface area and a non-reflection recess surface having a minimum surface area, thereby improving the brightness, changing the light path and improving the optical distribution and thus improving a displaying performance.

Abstract: Disclosed are an apparatus and a method for adaptively detecting received signals for power line communication, which are capable of stably receiving desired data transmitted via a power line irrespective of variations in channel characteristics.

Abstract: A static random access memory (SRAM) cell includes first and second load devices, first and second access transistors, first and second drive transistors, and two bit lines. The SRAM includes a substrate; an active region in the substrate, the active region being formed in a direction; gate electrodes of the first and second access transistors crossing the active region, the gate electrodes of the first and second access transistors are parallel with each other; gate electrodes of the first and second drive transistors crossing the active region, the gate electrodes of the first and second drive transistors are parallel with each other; and first and second load devices on the gate electrodes of the first and second access transistors, the first and second load devices are parallel with each other.

Abstract: A fabrication method for a capacitor having high capacitance that increases capacitance of a capacitor and consequently decreases defective semiconductor devices includes: forming a doped first polysilicon layer pattern on a semiconductor substrate; forming a silicide film pattern on the first polysilicon layer pattern; annealing the semiconductor substrate; sequentially forming a first insulating film and a second insulating film over the silicide film pattern; forming a contact hole to expose a portion of the silicide film pattern and then sequentially placing the semiconductor substrate in an etchant solution and a buffered etchant solution to remove a portion of the first insulating film formed on the silicide film pattern; forming a first capacitor electrode on a portion of an upper surface of the second insulating film pattern and the silicide film pattern, and at inner walls of the contact hole; and forming a dielectric layer on an outer surface of the lower electrode and then a second capacitor electr

Abstract: A method of fabricating an SRAM cell having a first conductivity type substrate includes the steps of forming a well of a second conductivity type in the first conductivity type substrate, forming a first active region of a first access transistor and a second active region of a second access transistor in the well, the first and second active regions being in parallel with each other, forming a first trench in the first active region and a second trench in the second active region, wherein the first and second trenches extend into the substrate through the well, forming gate electrodes of the first and second access transistors on the active regions, forming gate electrodes of first and second drive transistors in the first and second trenches, respectively, implanting first conductivity type impurity ions into the active regions of the first and second access transistors, respectively, forming first and second load devices on the substrate, the first and second load devices electrically contacting first ter

Abstract: A CMOS SRAM cell includes a substrate divided by a well trench into an n well region and a p well region, first and second active regions each having a V shape, formed symmetrical relative to each other, and having the well trench in between, third and fourth active regions formed symmetrically relative to each other and offset from the second active region, first and second gate lines each crossing the first active region, the well trench, and the second active region, and a third gate line crossing the third and fourth active regions.

Abstract: Static random access memory (SRAM) cell is disclosed, which is suitable for high packing density and cell stabilization, including a substrate, a wordline formed over the substrate, including two parallel legs having gates of first and second access transistors, respectively, gates of first and second drive transistors formed between the two parallel legs, and an active area defined in a surface of the substrate under the gates of the first and second access transistors and gates of the first and second drive transistors.

Abstract: A fabrication method for a capacitor having high capacitance that increases capacitance of a capacitor and consequently decreases defective semiconductor devices includes: forming a doped first polysilicon layer pattern on a semiconductor substrate; forming a silicide film pattern on the first polysilicon layer pattern; annealing the semiconductor substrate; sequentially forming a first insulating film and a second insulating film over the silicide film pattern; forming a contact hole to expose a portion of the silicide film pattern and then sequentially placing the semiconductor substrate in an etchant solution and a buffered etchant solution to remove a portion of the first insulating film formed on the silicide film pattern; forming a first capacitor electrode on a portion of an upper surface of the second insulating film pattern and the silicide film pattern, and at inner walls of the contact hole; and forming a dielectric layer on an outer surface of the lower electrode and then a second capacitor electr

Abstract: A static random access memory (SRAM) cell includes a substrate having first and second semiconductor layers, the second semiconductor layer being on the first semiconductor layer, active regions of first and second access transistors in the second semiconductor layer, gate electrodes of the first and second access transistors on the active regions, gate electrodes of first and second drive transistors in first terminals of the first and second access transistors, respectively, the gate electrodes penetrating the second semiconductor layer, first and second load resistors electrically contacting the first terminals of the first and second access transistors, respectively, and first and second bit lines electrically contacting second terminals of the first and second access transistors, respectively.

Abstract: The method for forming an insulating film having a low dielectric constant, which is suitable for intermetal insulating film applications, by plasma enhanced chemical vapor deposition (PECVD) includes the step of supplying a first source gas containing fluorine and carbon to a dual-frequency, high density plasma reactor. The method also includes the step of supplying a second source gas containing silicon dioxide to the reactor. In this manner a fluorocarbon/silicon dioxide film is formed on a substrate in the reactor.

Abstract: A static random access memory (SRAM) cell includes first and second load devices, first and second access transistors, first and second drive transistors, and two bit lines. The SRAM includes a substrate; an active region in the substrate, the active region being formed in a direction; gate electrodes of the first and second access transistors crossing the active region, the gate electrodes of the first and second access transistors are parallel with each other; gate electrodes of the first and second drive transistors crossing the active region, the gate electrodes of the first and second drive transistors are parallel with each other, and first and second load devices on the gate electrodes of the first and second access transistors, the first and second load devices are parallel with each other.