Patents by Inventor Dong-Wook Seo
Dong-Wook Seo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240129211Abstract: An apparatus for predicting a traffic speed and a method thereof are provided. The apparatus includes an input device that receives traffic speed sequences of a plurality of links and a controller that detects a spatio-temporal relationship between traffic speeds of the plurality of links and predicts a future traffic speed of a target link based on the spatio-temporal relationship between the traffic speeds of the plurality of links.Type: ApplicationFiled: March 6, 2023Publication date: April 18, 2024Inventors: Nam Hyuk Kim, Tae Heon Kim, Sung Hwan Park, Sang Wook Kim, Jun Ho Song, Ji Won Son, Dong Hyuk Seo
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Publication number: 20240097466Abstract: Disclosed is a high voltage output device having a serial-parallel stack structure of capacitors. The high voltage output device includes a substrate includes a capacitor element and a pillar structure provided on an upper surface of the substrate. The substrate includes a first electrode and a second electrode, which have different potentials from each other. The capacitor element is connected to at least one of the first electrode and the second electrode.Type: ApplicationFiled: November 16, 2023Publication date: March 21, 2024Applicant: JEISYS MEDICAL INC.Inventors: Seung Wook LEE, Seung In KANG, Yeong Gi JEON, Si Youn KIM, Kyu Young SEO, Min Young KIM, Won Ju YI, Dong Hwan KANG
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Patent number: 11927890Abstract: A substrate processing apparatus includes a photoresist coater applying a photoresist film on a substrate, a humidifier increasing an amount of moisture in an ambient to which the photoresist film on the substrate is exposed, and an exposer irradiating the photoresist film exposed to the ambient having the increased amount of moisture with light. The humidifier is disposed between the photoresist coater and the exposer.Type: GrantFiled: August 22, 2022Date of Patent: March 12, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seok Heo, Cha Won Koh, Sang Joon Hong, Hyun Woo Kim, Kyung-Won Kang, Dong-Wook Kim, Kyung Won Seo, Young Il Jang, Yong Suk Choi
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Patent number: 11854610Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.Type: GrantFiled: February 3, 2023Date of Patent: December 26, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Yeop Baeck, Tae-Hyung Kim, Daeyoung Moon, Dong-Wook Seo, Inhak Lee, Hyunsu Choi, Taejoong Song, Jae-Seung Choi, Jung-Myung Kang, Hoon Kim, Jisu Yu, Sun-Yung Jang
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Publication number: 20230337443Abstract: Provided are a three-dimensional (3D) semiconductor integrated circuit and a static random access memory (SRAM) device. The three-dimensional (3D) semiconductor integrated circuit includes: a first die including a power supply circuit a second die including an SRAM with a through-silicon-via (TSV) bundle region; a third die including a processor; and TSVs, each of which is provided on the TSV bundle region and extends from the TSV bundle region to the third die. The SRAM device includes: a bank array with banks, each of which includes sub-bit-cell arrays and a local peripheral circuit region arranged in a cross (+) shape between the sub-bit-cell arrays; and a global peripheral circuit region including a tail peripheral circuit region extending in a first direction and a head peripheral circuit region extending in a second direction, the tail peripheral circuit region and the head peripheral circuit region being arranged in a âTâ shape.Type: ApplicationFiled: March 27, 2023Publication date: October 19, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ho Young TANG, Tae-Hyung KIM, Dae Young MOON, Sang-Yeop BAECK, Dong-Wook SEO
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Publication number: 20230186982Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.Type: ApplicationFiled: February 3, 2023Publication date: June 15, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Yeop BAECK, Tae-Hyung KIM, Daeyoung MOON, Dong-Wook SEO, Inhak LEE, Hyunsu CHOI, Taejoong SONG, Jae-Seung CHOI, Jung-Myung Kang, Hoon KIM, Jisu YU, Sun-Yung JANG
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Patent number: 11581038Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.Type: GrantFiled: August 26, 2021Date of Patent: February 14, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Yeop Baeck, Tae-Hyung Kim, Daeyoung Moon, Dong-Wook Seo, Inhak Lee, Hyunsu Choi, Taejoong Song, Jae-Seung Choi, Jung-Myung Kang, Hoon Kim, Jisu Yu, Sun-Yung Jang
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Publication number: 20210383861Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.Type: ApplicationFiled: August 26, 2021Publication date: December 9, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Yeop BAECK, Tae-Hyung KIM, Daeyoung MOON, Dong-Wook SEO, Inhak LEE, Hyunsu CHOI, Taejoong SONG, Jae-Seung CHOI, Jung-Myung KANG, Hoon KIM, Jisu YU, Sun-Yung JANG
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Patent number: 11183233Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.Type: GrantFiled: September 10, 2019Date of Patent: November 23, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Yeop Baeck, Tae-Hyung Kim, Daeyoung Moon, Dong-Wook Seo, Inhak Lee, Hyunsu Choi, Taejoong Song, Jae-Seung Choi, Jung-Myung Kang, Hoon Kim, Jisu Yu, Sun-Yung Jang
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Patent number: 11152058Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.Type: GrantFiled: September 10, 2019Date of Patent: October 19, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Yeop Baeck, Tae-Hyung Kim, Daeyoung Moon, Dong-Wook Seo, Inhak Lee, Hyunsu Choi, Taejoong Song, Jae-Seung Choi, Jung-Myung Kang, Hoon Kim, Jisu Yu, Sun-Yung Jang
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Patent number: 11113368Abstract: An electronic device is provided.Type: GrantFiled: August 23, 2018Date of Patent: September 7, 2021Inventors: Dong-Wook Seo, Seong-Hun Moon, Moon-Kyung Kim, Myeong-Jin Oh, Se-Yeong Lee, Da-Som Lee
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Patent number: 10672442Abstract: Provided are a voltage control circuit including an assist circuit and a memory device including the voltage control circuit. The memory device includes: a volatile memory cell array, which is connected to a plurality of word lines and includes a memory cell including at least one transistor; and an assist circuit, which is connected to at least one of the plurality of word lines and adjusts a driving voltage level of each of the plurality of word lines, wherein the assist circuit includes a diode N-channel metal oxide semiconductor (NMOS) transistor having a gate and a drain connected to each other.Type: GrantFiled: August 29, 2019Date of Patent: June 2, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-yeop Baeck, Siddharth Gupta, In-hak Lee, Jae-seung Choi, Tae-hyung Kim, Dae-young Moon, Dong-wook Seo
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Publication number: 20200005860Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.Type: ApplicationFiled: September 10, 2019Publication date: January 2, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Yeop BAECK, Tae-Hyung KIM, Daeyoung MOON, Dong-Wook SEO, Inhak LEE, Hyunsu CHOI, Taejoong SONG, Jae-Seung CHOI, Jung-Myung KANG, Hoon KIM, Jisu YU, Sun-Yung JANG
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Publication number: 20190385653Abstract: Provided are a voltage control circuit including an assist circuit and a memory device including the voltage control circuit. The memory device includes: a volatile memory cell array, which is connected to a plurality of word lines and includes a memory cell including at least one transistor; and an assist circuit, which is connected to at least one of the plurality of word lines and adjusts a driving voltage level of each of the plurality of word lines, wherein the assist circuit includes a diode N-channel metal oxide semiconductor (NMOS) transistor having a gate and a drain connected to each other.Type: ApplicationFiled: August 29, 2019Publication date: December 19, 2019Inventors: Sang-Yeop BAECK, Siddharth Gupta, ln-hak Lee, Jae-seung Choi, Tae-hyung Kim, Dae-young Moon, Dong-wook Seo
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Patent number: 10453521Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.Type: GrantFiled: January 27, 2017Date of Patent: October 22, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Yeop Baeck, Tae-Hyung Kim, Daeyoung Moon, Dong-Wook Seo, Inhak Lee, Hyunsu Choi, Taejoong Song, Jae-Seung Choi, Jung-Myung Kang, Hoon Kim, Jisu Yu, Sun-Yung Jang
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Patent number: 10431272Abstract: Provided are a voltage control circuit including an assist circuit and a memory device including the voltage control circuit. The memory device includes: a volatile memory cell array, which is connected to a plurality of word lines and includes a memory cell including at least one transistor; and an assist circuit, which is connected to at least one of the plurality of word lines and adjusts a driving voltage level of each of the plurality of word lines, wherein the assist circuit includes a diode N-channel metal oxide semiconductor (NMOS) transistor having a gate and a drain connected to each other.Type: GrantFiled: March 15, 2018Date of Patent: October 1, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-yeop Baeck, Siddharth Gupta, In-hak Lee, Jae-seung Choi, Tae-hyung Kim, Dae-young Moon, Dong-wook Seo
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Patent number: 10236056Abstract: A volatile memory device includes a memory cell array configured to be supplied with a first power supply voltage through a first power supply line, and configured to store data based on the first power supply line; and a peripheral circuit configured to be supplied with a second power supply voltage through a second power supply line, and configured to control the memory cell array based on the second power supply line, the peripheral circuit including a self timing pulse circuit configured to determine an operation timing of the peripheral circuit, the self timing pulse circuit configured to be supplied with the first power supply voltage through the first power supply line, and the self timing pulse circuit being configured to adjust the operation timing of the peripheral circuit according to the voltage level of the first power supply voltage.Type: GrantFiled: February 9, 2017Date of Patent: March 19, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Wook Seo, Jae-Seung Choi, Hyun-Su Choi
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Publication number: 20190080736Abstract: Provided are a voltage control circuit including an assist circuit and a memory device including the voltage control circuit. The memory device includes: a volatile memory cell array, which is connected to a plurality of word lines and includes a memory cell including at least one transistor; and an assist circuit, which is connected to at least one of the plurality of word lines and adjusts a driving voltage level of each of the plurality of word lines, wherein the assist circuit includes a diode N-channel metal oxide semiconductor (NMOS) transistor having a gate and a drain connected to each other.Type: ApplicationFiled: March 15, 2018Publication date: March 14, 2019Inventors: Sang-yeop Baeck, Siddharth Gupta, In-hak Lee, Jae-seung Choi, Tae-hyung Kim, Dae-young Moon, Dong-wook Seo
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Publication number: 20190065711Abstract: An electronic device is provided.Type: ApplicationFiled: August 23, 2018Publication date: February 28, 2019Inventors: Dong-Wook Seo, Seong-Hun Moon, Moon-Kyung Kim, Myeong-Jin Oh, Se-Yeong Lee, Da-Som Lee
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Patent number: 9897655Abstract: A scan chain circuit includes first through N-th flip-flops connected in series to sequentially transfer data in response to a control signal, where N is an integer greater than 1. In the first through N-th flip-flops, the data are transferred in a first direction from the first flip-flop to the N-th flip-flop. The control signal is applied to the first through N-th flip-flops in a second direction opposite to the first direction from the N-th flip-flop to the first flip-flop.Type: GrantFiled: May 7, 2015Date of Patent: February 20, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: In-Gyu Park, Dong-Wook Seo, Chan-Ho Lee