Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.

Abstract: A volatile memory device includes a memory cell array configured to be supplied with a first power supply voltage through a first power supply line, and configured to store data based on the first power supply line; and a peripheral circuit configured to be supplied with a second power supply voltage through a second power supply line, and configured to control the memory cell array based on the second power supply line, the peripheral circuit including a self timing pulse circuit configured to determine an operation timing of the peripheral circuit, the self timing pulse circuit configured to be supplied with the first power supply voltage through the first power supply line, and the self timing pulse circuit being configured to adjust the operation timing of the peripheral circuit according to the voltage level of the first power supply voltage.

Abstract: A volatile memory device includes a memory cell array configured to be supplied with a first power supply voltage through a first power supply line, and configured to store data based on the first power supply line; and a peripheral circuit configured to be supplied with a second power supply voltage through a second power supply line, and configured to control the memory cell array based on the second power supply line, the peripheral circuit including a self timing pulse circuit configured to determine an operation timing of the peripheral circuit, the self timing pulse circuit configured to be supplied with the first power supply voltage through the first power supply line, and the self timing pulse circuit being configured to adjust the operation timing of the peripheral circuit according to the voltage level of the first power supply voltage.

Abstract: Systems and method for reading data samples in reverse group order are described herein according to various embodiments of the present disclosure. In one embodiment, a method for reading data samples in a memory is provided, wherein the data samples correspond to an operand of a vector operation, the data samples are grouped into a plurality of different groups, and the different groups are spaced apart by a plurality of addresses in the memory. The method comprises reading the groups of data samples in reverse group order, and, for each group, reading the data samples in the group in forward order.

Abstract: A scan chain circuit includes first through N-th flip-flops connected in series to sequentially transfer data in response to a control signal, where N is an integer greater than 1. In the first through N-th flip-flops, the data are transferred in a first direction from the first flip-flop to the N-th flip-flop. The control signal is applied to the first through N-th flip-flops in a second direction opposite to the first direction from the N-th flip-flop to the first flip-flop.

Abstract: A volatile memory device includes a memory cell array configured to be supplied with a first power supply voltage through a first power supply line, and configured to store data based on the first power supply line; and a peripheral circuit configured to be supplied with a second power supply voltage through a second power supply line, and configured to control the memory cell array based on the second power supply line, the peripheral circuit including a self timing pulse circuit configured to determine an operation timing of the peripheral circuit, the self timing pulse circuit configured to be supplied with the first power supply voltage through the first power supply line, and the self timing pulse circuit being configured to adjust the operation timing of the peripheral circuit according to the voltage level of the first power supply voltage.

Abstract: Systems and methods for generating twiddle factors are described herein according to various embodiments of the present disclosure. In one embodiment, a method for twiddle factor generation comprises generating a first twiddle phase, wherein the first twiddle phase is from a set of radix-M1 twiddle phases, and M1 is an integer. The method also comprises converting the first twiddle phase into a second twiddle phase, wherein the second twiddle phase is from a set of radix-M2 twiddle phases, and M2 is an integer that is different from M1. The method further comprises generating a twiddle factor based on the second twiddle phase.

Abstract: Systems and method for reading data samples in reverse group order are described herein according to various embodiments of the present disclosure. In one embodiment, a method for reading data samples in a memory is provided, wherein the data samples correspond to an operand of a vector operation, the data samples are grouped into a plurality of different groups, and the different groups are spaced apart by a plurality of addresses in the memory. The method comprises reading the groups of data samples in reverse group order, and, for each group, reading the data samples in the group in forward order.

Abstract: A system on chip includes an SRAM. The SRAM includes at least one memory cell and a peripheral circuit accessing the at least memory cell. A first power circuit is configured to supply a first driving voltage to the at least one memory cell. A second power circuit is configured to supply a second driving voltage to the peripheral circuit. The SRAM further includes an auto power switch that selects the higher of the first driving voltage and the second driving voltage and supplies the selected voltage to the at least one memory cell.

Abstract: A system on chip includes an SRAM. The SRAM includes at least one memory cell and a peripheral circuit accessing the at least memory cell. A first power circuit is configured to supply a first driving voltage to the at least one memory cell. A second power circuit is configured to supply a second driving voltage to the peripheral circuit. The SRAM further includes an auto power switch that selects the higher of the first driving voltage and the second driving voltage and supplies the selected voltage to the at least one memory cell.

Abstract: A method for controlling operation of a receiver may include: generating an operation control signal based on a signal-to-noise ratio (SNR) value of an Nth symbol, wherein N is a natural number, of a hopping pattern included in a preamble of a packet; and controlling whether an Nth symbol of each hopping pattern included in a header or payload of the packet may be processed in response to the operation control signal. A receiver may include: an operation control signal generator that may generate an operation control signal based on a signal-to-noise ratio (SNR) value of an Nth symbol, where N is a natural number, of a hopping pattern included in a preamble of a packet; and a receiving unit that may control whether an Nth symbol of each hopping pattern included in a header or payload of the packet is processed in response to the operation control signal.

Abstract: A method and mobile device for decoding a paging message transmitted as multiple bursts in a wireless communication system are provided. In the method, only the first burst among four bursts of a transmitted paging message is received and equalized. The equalized first burst is compared (e.g., by computing correlation) with a reference paging message. The first comparison result value obtained from the first comparison is compared with a threshold value. If the first comparison result value is greater than the threshold value, second through fourth bursts of the paging message are not received, and a previous decoded paging message is output and a sleep state is entered. If the comparison result value is not greater than the threshold value, the second through fourth bursts are received and decoded, the decoded paging message is encoded, and a first burst of the encoded paging message is stored as the reference paging message.

Abstract: A method of decoding a control channel in a wireless communication system is provided. In the method, a terminal calculates the number of sub-bursts to be used during a next decoding and positions of the sub-bursts, based on a signal-to-noise ratio of at least one of a first burst or a second burst. Then, the terminal compares the calculated number of sub-bursts with a reference value. When the calculated number of sub-bursts is greater than the reference value, the terminal does not receive more bursts or sub-bursts and instead enters into a sleep state. When the calculated number of sub-bursts is smaller than or equal to the reference value, the terminal receives and decodes only sub-bursts at the calculated positions.

Abstract: An integrated circuit device includes a memory array having a multi-port memory cell (e.g., dual-port SRAM cell) therein. This multi-port memory cell includes at least first and second read/write ports, which may be provided by respective access transistors (e.g., N-type MOS transistors) that are responsive to word line signals. The first and second read/write ports are electrically coupled to the first and second bit lines, respectively. A first clipping circuit is also provided. The first clipping circuit is responsive to a first write control signal. The first clipping circuit is configured to bias the first bit line with a read blocking voltage during a first “overlapping” operation to write data from the second bit line into the multi-port memory cell concurrently with reading data from the multi-port memory cell onto the first bit line.

Abstract: A power gating circuit of a memory device includes a power gating unit and a control unit. The power gating unit includes first, second, and third power gating transistors connected in parallel between a power supply voltage and an internal power supply voltage bus of the memory device. The three power gating transistors are sequentially turned ON. The second and third power gating transistors turn ON sequentially in response to the increasing voltage level of the bus. The timing points when the second and third power gating transistors are sequentially turned ON is based upon detecting the gradually increasing the voltage level of the internal power supply voltage. The size of the first power gating transistor may be smaller than the size of the second power gating transistor, and the size of the second power gating transistor may be smaller than the size of the third power gating transistor.

Abstract: A method of reducing a number of computations in an equalization process includes performing a pre-equalization operation on selected first frames from a plurality of frames, and estimating pre-equalization values of second frames based on the pre-equalization values of selected first frames, the second frames being frames which are not selected from the plurality of frames.

Abstract: An integrated circuit device includes a memory array having a multi-port memory cell (e.g., dual-port SRAM cell) therein. This multi-port memory cell includes at least first and second read/write ports, which may be provided by respective access transistors (e.g., N-type MOS transistors) that are responsive to word line signals. The first and second read/write ports are electrically coupled to the first and second bit lines, respectively. A first clipping circuit is also provided. The first clipping circuit is responsive to a first write control signal. The first clipping circuit is configured to bias the first bit line with a read blocking voltage during a first “overlapping” operation to write data from the second bit line into the multi-port memory cell concurrently with reading data from the multi-port memory cell onto the first bit line.

Abstract: A memory device having a short precharge time is included. The memory device selects at least two pairs of bit lines and connects the selected two pairs of bit lines to the sense amplifier within a preparatory period during which the two pairs of bit lines and an input to the sense amplifier are precharged. In the preparatory period an input unit of the sense amplifier is precharged through by a plurality of precharge units through more than two bit lines, and thus the precharge time may be decreased. The memory device selects one pair of bit lines and connects the selected pair of bit lines to a sense amplifier within a read/write (data transmission) period.

Abstract: A method for controlling operation of a receiver may include: generating an operation control signal based on a signal-to-noise ratio (SNR) value of an Nth symbol, wherein N is a natural number, of a hopping pattern included in a preamble of a packet; and controlling whether an Nth symbol of each hopping pattern included in a header or payload of the packet may be processed in response to the operation control signal. A receiver may include: an operation control signal generator that may generate an operation control signal based on a signal-to-noise ratio (SNR) value of an Nth symbol, where N is a natural number, of a hopping pattern included in a preamble of a packet; and a receiving unit that may control whether an Nth symbol of each hopping pattern included in a header or payload of the packet is processed in response to the operation control signal.

Abstract: The characteristics of this invention consist of the following stages: the consumer connects to wire or wireless internet, mobile communication network, or digital broadcasting network through his/her terminal device; the consumer searches for and selects music and multimedia data; the consumer appoints the output device for the selected music and multimedia data; the music or multimedia data is played by the above selected output device; and the consumer and related business end settles the charges.