Abstract: A memory system may include: a memory device comprising a plurality of memory dies; and a controller configured to perform: analyzing a first and second commands when the first and second commands are sequentially transferred to any one selected memory die of the plurality of memory dies, identifying first and third operations of the first command and second and fourth operations of the second command, calculating a single power which is expected to be used in one or more single operation sections in which only any one respective operation of the first to fourth operations is performed, calculating an overlap power which is expected to be used in one or more overlap operation sections in which a respective plurality of operations of the first to fourth operations are performed while overlapping each other, calculating a total power which is expected to be used when the first and second commands are performed in the selected memory die by adding the single power and the overlap power according to operation tim

Abstract: A memory system containing: a nonvolatile memory device including a plurality of memory dies that each perform a plurality of command operations, and a controller configured to: store, in a preset internal space, profile information for changes in power consumption for each of a operation sections included in each of the command operations, check, from the profile information, the changes in power consumption for each operation section of a first and second command when sequentially propagating the first and second command to the memory dies, calculate, based on the checked changes in power consumption for each operation section, a maximum length of an overlap operation section between the first and second command in which peak power is maintained at or below a first reference power, and adjust, a difference between time points for performing the first and second command based on the calculated maximum length of the overlap operation section.

Abstract: A memory system, comprising: a nonvolatile memory device including a plurality of memory dies that each perform a plurality of command operations, and a controller is configured to: store, in a preset internal space, profile information for changes in power consumption for each of a operation sections included in each of the command operations, check, from the profile information, the changes in power consumption for each operation section of a first and second command when sequentially propagating the first and second command to the memory dies, calculate, based on the checked changes in power consumption for each operation section, a maximum length of an overlap operation section between the first and second command in which peak power is maintained at or below a first reference power, and adjust, a difference between time points for performing the first and second command based on the calculated maximum length of the overlap operation section.

Abstract: A memory controller includes a central processing unit (CPU) configured to translate a logical address corresponding to an operation that is to be performed by a memory device into a physical address, and an addressing component configured to acquire information about an addressing rule supported by the memory device, among a plurality of addressing rules, and to configure an addressing table corresponding to the operation using the acquired addressing rule information and the physical address.

Abstract: A memory system may include: a memory device comprising a plurality of memory dies; and a controller configured to perform: analyzing a first and second commands when the first and second commands are sequentially transferred to any one selected memory die of the plurality of memory dies, identifying first and third operations of the first command and second and fourth operations of the second command, calculating a single power which is expected to be used in one or more single operation sections in which only any one respective operation of the first to fourth operations is performed, calculating an overlap power which is expected to be used in one or more overlap operation sections in which a respective plurality of operations of the first to fourth operations are performed while overlapping each other, calculating a total power which is expected to be used when the first and second commands are performed in the selected memory die by adding the single power and the overlap power according to operation tim

Abstract: There are provided a memory system and an operating method thereof. A memory system includes a plurality of memory devices for performing operations, a power consumption profile table storing section for storing a power consumption profile table of power consumption values with respect to times when the memory devices perform the operations, and a processor for deriving a total power consumption value for the plurality of memory devices based on the power consumption profile table, and determining whether to release or hold a queued command based on the derived total power consumption value.

Abstract: A data storage device includes a nonvolatile memory device including dies; and a controller. The controller includes a processor configured to transmit operation commands to the nonvolatile memory device, and output control signals instructing to generate power consumption profiles for dies which operate; and a power management unit configured to operate according to the control signals. The power management unit includes a power profile command table in which power profile commands corresponding to each of the operation commands are stored; a power profile command processing circuit configured to generate the power consumption profiles, by processing the power profile commands corresponding to each control signal; and a power budget scheduler configured to determine whether to transmit the operation commands to the nonvolatile memory device, depending on a total power consumption amount summed at each set unit time based on the power consumption profiles.

Abstract: A memory system may include: a plurality of resources; and a frequency adjuster configured to adjust operating frequencies of the plurality of resources at a predetermined adjustment timing, wherein the adjustment timing comprises at least one timing for dividing partial operation periods of at least one resource among the plurality of resources.

Abstract: Provided herein may be an electronic device, a memory system having the electronic device, and an operating method thereof. The electronic device may include a voltage manager configured to determine whether a voltage abnormality occurs by monitoring a voltage to be supplied to a target device, and an operation manager configured to perform an operation control of the target device, and re-perform, when the voltage manager determines that the voltage abnormality has occurred, the operation control being performed at a time of the occurrence of the voltage abnormality.

Abstract: An electronic apparatus includes a data storage device including a plurality of plane groups and a controller configured to control the data storage device. The controller includes a temporary storage configured to store a command received from a host apparatus, a processor configured to define a plurality of queue regions corresponding to the plurality of plane groups within the temporary storage, and queue the command for each of the plurality of plane groups to a queue region matching with a corresponding plane group, and a plurality of pointer registers corresponding to the plurality of queue region, respectively, and configured to indicate positions of the plurality of queue regions. The processor changes a number of the queue regions, sizes of the queue regions, and sizes of the pointer registers according to a number of the plane groups.

Abstract: A memory system includes: a memory device including a plurality of pages; and a controller suitable for generating a read descriptor in response to an entered command, reading and outputting read data stored in at least one page in response to the read descriptor, determining whether each per-page data of the read data includes an error, storing indicators for showing whether each per-page data includes the error, re-reading some of the read data on per-page basis, based on the indicators, without generating another read descriptor, and updating the indicators based on an error check result after the re-reading.

Abstract: There are provided a memory controller, a memory system including the memory controller, and a method of operating the memory controller. In a memory controller for accessing a plurality of memories in response to a request from a host, the memory controller includes: a processor for generating a command set, based on command generation information of a selected memory among the plurality of memories; and a storage circuit for storing command generation information of each of the plurality of memories.

Abstract: There are provided a memory controller, a memory system having the memory controller, and an operating method of the memory controller. The memory controller includes a status check command determining section for checking a status check command supported by a memory device among a plurality of status check commands, and a status check performing section for performing a status check operation on the memory device by using the checked status check command.

Abstract: Provided herein may be a memory system and a method of operating the memory system. The memory system may include: a nonvolatile memory device configured to perform internal operations in response to command/address sequences; and a memory controller configured to provide the command/address sequences to the nonvolatile memory device. The memory controller may include: a firmware section configured to manage read/write characteristic information about the nonvolatile memory device; and a hardware section configured to generate command/address sequences based on the read/write characteristic information.

Abstract: A data storage device includes: a storage configured to generate a program completion signal when a data chunk is completely programmed; a buffer memory having a plurality of buffer regions configured to cache a plurality of data chunks, respectively; and a controller configured to receive a data chunk from a host device while a previously cached data chunk in the buffer memory is programmed to the storage; cache the received data chunk into the buffer memory; delete the programmed data chunk from the buffer memory in response to the program completion signal; receive a new data chunk from the host device; and cache the received new data chunk in an empty buffer region of the buffer memory.

Abstract: A semiconductor memory device includes a memory cell array, a peripheral circuit, a ready busy signal generator, and a control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit is configured to perform one of a read operation, a write operation, and an erase operation on the memory cell array. The ready busy signal generator is configured to selectively output one of an internal ready busy signal and an external ready busy signal according to an operation of the semiconductor memory device. The control logic is configured to control operations of the peripheral circuit and the ready busy signal generator.

Abstract: A memory system includes: a memory device comprising a plurality of memory dies in which command operations corresponding to a plurality of commands received from a host are performed; and a controller suitable for issuing RS (Read Status) commands to memory dies included in a first memory die group among the memory dies, issuing the RS commands to memory dies included in a second memory die group, checking whether the command operations are performed in the memory dies, through responses to the RS commands, and resetting an issue period of the RS commands in response to a change of the memory dies to which the RS commands are issued.

Abstract: Provided herein may be an electronic device, a memory system having the electronic device, and an operating method thereof. The electronic device may include a voltage manager configured to determine whether a voltage abnormality occurs by monitoring a voltage to be supplied to a target device, and an operation manager configured to perform an operation control of the target device, and re-perform, when the voltage manager determines that the voltage abnormality has occurred, the operation control being performed at a time of the occurrence of the voltage abnormality.

Abstract: A memory controller includes a central processing unit (CPU) configured to translate a logical address corresponding to an operation that is to be performed by a memory device into a physical address, and an addressing component configured to acquire information about an addressing rule supported by the memory device, among a plurality of addressing rules, and to configure an addressing table corresponding to the operation using the acquired addressing rule information and the physical address.

Abstract: A data storage device includes a nonvolatile memory device including dies; and a controller. The controller includes a processor configured to transmit operation commands to the nonvolatile memory device, and output control signals instructing to generate power consumption profiles for dies which operate; and a power management unit configured to operate according to the control signals. The power management unit includes a power profile command table in which power profile commands corresponding to each of the operation commands are stored; a power profile command processing circuit configured to generate the power consumption profiles, by processing the power profile commands corresponding to each control signal; and a power budget scheduler configured to determine whether to transmit the operation commands to the nonvolatile memory device, depending on a total power consumption amount summed at each set unit time based on the power consumption profiles.