Abstract: An electronic apparatus includes a data storage device including a plurality of plane groups and a controller configured to control the data storage device. The controller includes a temporary storage configured to store a command received from a host apparatus, a processor configured to define a plurality of queue regions corresponding to the plurality of plane groups within the temporary storage, and queue the command for each of the plurality of plane groups to a queue region matching with a corresponding plane group, and a plurality of pointer registers corresponding to the plurality of queue region, respectively, and configured to indicate positions of the plurality of queue regions. The processor changes a number of the queue regions, sizes of the queue regions, and sizes of the pointer registers according to a number of the plane groups.

Abstract: There are provided a memory controller, a memory system having the memory controller, and an operating method of the memory controller. The memory controller includes a status check command determining section for checking a status check command supported by a memory device among a plurality of status check commands, and a status check performing section for performing a status check operation on the memory device by using the checked status check command.

Abstract: A memory system may include: a plurality of resources; and a frequency adjuster configured to adjust operating frequencies of the plurality of resources at a predetermined adjustment timing, wherein the adjustment timing comprises at least one timing for dividing partial operation periods of at least one resource among the plurality of resources.

Abstract: A data storage device includes nonvolatile memory devices coupled to a plurality of channels; and a controller including a processor, a buffer and memory controllers which are respectively coupled to the channels, wherein the processor transmits a first access command to a first memory controller in response to a first access request from a host device, regardless of a state of the buffer, and wherein the first memory controller controls an internal operation of a first nonvolatile memory device by determining the state of the buffer, in response to the first access command.

Abstract: A data storage device includes a nonvolatile memory device; a control unit suitable for generating a descriptor in which works for controlling the nonvolatile memory device are described; a memory control unit suitable for performing a control operation for the nonvolatile memory device and a data input operation, based on the descriptor; and a calibrator suitable for performing a calibration operation for a signal to be provided to the nonvolatile memory device, in response to an enable signal provided from the memory control unit, wherein the memory control unit controls the calibrator such that the control operation for the nonvolatile memory device and the calibration operation of the calibrator are performed in parallel.

Abstract: There are provided a memory system and an operating method thereof. A memory system includes a plurality of memory devices for performing operations, a power consumption profile table storing section for storing a power consumption profile table of power consumption values with respect to times when the memory devices perform the operations, and a processor for deriving a total power consumption value for the plurality of memory devices based on the power consumption profile table, and determining whether to release or hold a queued command based on the derived total power consumption value.

Abstract: Provided herein may be a memory system and a method of operating the memory system. The memory system may include: a nonvolatile memory device configured to perform internal operations in response to command/address sequences; and a memory controller configured to provide the command/address sequences to the nonvolatile memory device. The memory controller may include: a firmware section configured to manage read/write characteristic information about the nonvolatile memory device; and a hardware section configured to generate command/address sequences based on the read/write characteristic information.

Abstract: A memory system includes: a memory device including a plurality of pages; and a controller suitable for generating a read descriptor in response to an entered command, reading and outputting read data stored in at least one page in response to the read descriptor, determining whether each per-page data of the read data includes an error, storing indicators for showing whether each per-page data includes the error, re-reading some of the read data on per-page basis, based on the indicators, without generating another read descriptor, and updating the indicators based on an error check result after the re-reading.

Abstract: There are provided a memory controller, a memory system including the memory controller, and a method of operating the memory controller. In a memory controller for accessing a plurality of memories in response to a request from a host, the memory controller includes: a processor for generating a command set, based on command generation information of a selected memory among the plurality of memories; and a storage circuit for storing command generation information of each of the plurality of memories.

Abstract: A data storage device includes: a plurality of nonvolatile memory devices; and a controller suitable for receiving a command and executing the command for the plurality of nonvolatile memory devices. The controller includes: a first queue suitable for storing the command; and a command manager suitable for managing the command in the first queue, based on a first attribute of the command and queue information of the first queue.

Abstract: A semiconductor memory device includes a memory cell array, a peripheral circuit, a ready busy signal generator, and a control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit is configured to perform one of a read operation, a write operation, and an erase operation on the memory cell array. The read busy signal generator is configured to selectively output one of an internal ready busy signal and an external ready busy signal according to an operation of the semiconductor memory device. The control logic is configured to control operations of the peripheral circuit and the ready busy signal generator.

Abstract: In accordance with an embodiment of the present invention, a controller may include a buffer for storing a plurality of commands in accordance with an input order; a setting unit for setting order information of a read status check operation to be performed on respective storage devices corresponding to the plurality of commands, wherein the storage devices are included in a memory device; a performing unit for controlling the memory device to sequentially perform the read status check operation based on the order information; and a processor for controlling the memory device to perform a command operation in response to the plurality of commands based on a result of the read status check operation.

Abstract: A memory system includes: one or more memory devices each including a plurality of memory dies each having a plurality of planes; and a controller including: a random command queue suitable for queueing a plurality of random read commands; a multi-read command queue suitable for queueing at least merged random read commands; a read rule checker suitable for storing a multi-read rule representing a direction for selecting two or more among the planes; a command arbitrator suitable for merging two or more random read commands satisfying the multi-read rule among the random read commands queued in the random read commands, and queueing at least the merged random read commands in the multi-read command queue; and a processor suitable for controlling the memory devices to perform a multi-plane read operation according to the merged random read commands in the multi-read command queue.

Abstract: The memory system may include a memory device including a plurality of sub-memory devices coupled to a channel; and a controller suitable for controlling the memory device to store a first data into a selected sub-memory device and at least one idle sub-memory device among the sub-memory devices during a first program operation to a selected sub-memory device among the sub-memory devices with the first data with a first data; and to perform a second program operation to the selected sub-memory device with the first data stored in the idle sub-memory device when the first program operation to the selected sub-memory device fails.

Abstract: A data storage device includes a nonvolatile memory device; a control unit suitable for generating a descriptor in which works for controlling the nonvolatile memory device are described; a memory control unit suitable for performing a control operation for the nonvolatile memory device and a data input operation, based on the descriptor; and a calibrator suitable for performing a calibration operation for a signal to be provided to the nonvolatile memory device, in response to an enable signal provided from the memory control unit, wherein the memory control unit controls the calibrator such that the control operation for the nonvolatile memory device and the calibration operation of the calibrator are performed in parallel.

Abstract: A memory system includes: a memory device comprising a plurality of memory dies in which command operations corresponding to a plurality of commands received from a host are performed; and a controller suitable for issuing RS (Read Status) commands to memory dies included in a first memory die group among the memory dies, issuing the RS commands to memory dies included in a second memory die group, checking whether the command operations are performed in the memory dies, through responses to the RS commands, and resetting an issue period of the RS commands in response to a change of the memory dies to which the RS commands are issued.

Abstract: A data storage device includes nonvolatile memory devices coupled to a plurality of channels; and a controller including a processor, a buffer and memory controllers which are respectively coupled to the channels, wherein the processor transmits a first access command to a first memory controller in response to a first access request from a host device, regardless of a state of the buffer, and wherein the first memory controller controls an internal operation of a first nonvolatile memory device by determining the state of the buffer, in response to the first access command.

Abstract: Disclosed is a storage device, including: a memory controller configured to generate mode maintenance information or mode change information in response to a command received from a host; and a memory device configured to perform a selected operation in a previous mode when the mode maintenance information is received, and change a mode and perform the selected operation when the mode change information is received.

Abstract: A data storage device includes: a plurality of nonvolatile memory devices; and a controller suitable for receiving a command and executing the command for the plurality of nonvolatile memory devices. The controller includes: a first queue suitable for storing the command; and a command manager suitable for managing the command in the first queue, based on a first attribute of the command and queue information of the first queue.

Abstract: There are provided a memory system and an operating method thereof. A memory system includes a memory device suitable for storing data therein; and a memory controller suitable for initializing the memory device, or maintaining or changing a mode of the memory device according to power of the memory device during a wake-up operation.