Patents by Inventor Dong Yu He

Dong Yu He has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220191507
    Abstract: A method for compressing video signals based on adaptive compression rate and a circuit system thereof are provided. In the method, a digital signal processor is used to process a video so as to frame-by-frame obtain statistical data, for example, a maximum of compressed data. The maximum of compressed data of a previous frame is used to determine a compression state of a current frame. The compression state of the frame allows the processor to decide a direction to adjust a compression ratio. Next, statistical data of the previous frame is used to decide a stride to adjust the compression ratio. The statistical data can be a maximum of compressed data and a quantization table scale referred to rendering a prediction curve that allows the processor to determine the stride. A compression ratio is then determined according to the direction and the stride of adjustment.
    Type: Application
    Filed: December 13, 2021
    Publication date: June 16, 2022
    Inventors: DONG-YU HE, JING SUN, JIAN SUN
  • Publication number: 20220191382
    Abstract: The present disclosure discloses an image flicker detection method that includes the steps outlined below. An image retrieving is performed to retrieve a current image. A current variation ratio between first rows of pixels of the current image and second rows of pixels in a previous image is calculated. When both the current variation ratio and a previous variation ratio are determined to be larger than a ratio threshold, a detected flicker number is incremented. When the detected flicker number is determined to be larger than a flicker number threshold, a flicker condition is determined to occur. When the detected flicker number is determined to be not larger than the flicker number threshold, the current image becomes the previous image and the current variation ratio becomes the previous variation ratio such that a next image becomes the current image to repeat the above steps.
    Type: Application
    Filed: June 23, 2021
    Publication date: June 16, 2022
    Inventors: XIAO-YU CHEN, DONG-YU HE, YANG LU, GANG SHEN
  • Publication number: 20220014414
    Abstract: A method for authentication data transmission and a system thereof are provided. The method is operated in a computer system that is connected to a biometric device, and a secure channel is established there-between according to a security protocol. The computer system can receive encrypted biometric feature data from the biometric device based on a request. In a secure environment built in the computer system, the biometric feature data is decrypted and biometric features can be extracted. A comparison result is generated after comparing the biometric features with feature data in a database. The comparison result can be transmitted to the biometric device. The comparison result is then encrypted in the biometric device according to the security protocol.
    Type: Application
    Filed: May 11, 2021
    Publication date: January 13, 2022
    Inventors: HONG-HAI DAI, YANG LI, DONG-YU HE, JIAYUAN TAN
  • Publication number: 20220005167
    Abstract: The present disclosure discloses a multi-path image processing apparatus. An image merging circuit is configured to receive image frames that at least one of the image frames has a largest row number, generate redundant pixel row for each of the image frames that has a row number smaller than the largest row number such that the row number of each of the image frames equals to the largest row number, generate redundant pixel columns for each of the image frames having the number thereof determined by a size of a largest operation window, and merge each two of the image frames through the redundant columns thereof to generate a merged image frame. An image processing circuit performs image processing procedure on the merged image frame to generate a processed merged image frame, wherein at least a part of the image processing procedure is operated according to the largest operation window. An image segmentation circuit segments the processed merged image frame to generate processed image frames.
    Type: Application
    Filed: December 23, 2020
    Publication date: January 6, 2022
    Inventors: QING-ZHE QIU, DONG-YU HE, SHAO-HUA JIN, HONG-HAI DAI
  • Publication number: 20210397441
    Abstract: A firmware updating system and method are provided. The firmware updating method includes configuring a host to digitally sign a firmware to be updated, and configuring an electronic device to perform an authorization verification on an update tool, and only the update tool that passes the verification has an update permission. The update tool uses an encryption algorithm to encrypt the firmware to be updated that includes a digital signature. After the encryption is completed, the host sends the update tool to the electronic device through the update tool. The electronic device then uses a decryption algorithm to decrypt the received firmware to obtain the firmware to be updated including the digital signature, and write the firmware to be updated into a firmware storage area to be updated. The electronic device then verifies the digital signature in the firmware to be updated.
    Type: Application
    Filed: April 15, 2021
    Publication date: December 23, 2021
    Inventors: DONG-YU HE, MENG-YAO GU, JIAN SUN
  • Patent number: 10986322
    Abstract: An image white balance processing method is provided. The image white balance processing method includes: calculating color coordinate points; when it is determined that the color coordinate points are in a first given region, calculating a plurality of weighted averages according to a plurality of coordinate components and a plurality of weight values of color coordinate points of a white given image region, and when it is determined that the color coordinate points are in a second given region, calculating a plurality of averages according to a plurality of coordinate components of color coordinate points of a green given image region; calculating an estimated coordinate point; and calculating a plurality of white balance gains according to the number of a plurality of white given image regions and green given image regions, the plurality of weighted averages, and the estimated coordinate point to compensate for the plurality of given image regions.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: April 20, 2021
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Xiao-Yu Chen, Gang Shen, Yang Lu, Dong-Yu He
  • Publication number: 20190212930
    Abstract: This invention discloses a data storage chip and a data access method. The data access method is applied to a memory that includes a first area having a first range of memory address and a second area having a second range of memory address. The first range of memory address and the second range of memory address do not overlap. The method includes steps of: reading a predetermined address of the first area to obtain a control value; receiving a memory read command containing a target address; accessing the first area according to the memory read command when the target address is within the first range of memory address, and accessing the second area according to the memory read command when the target address is within the second range of memory address; and selectively sending the data read from the first area according to the control value.
    Type: Application
    Filed: December 18, 2018
    Publication date: July 11, 2019
    Inventors: ZHENBING QIAN, DONG-YU HE, XIN YIN, ZHAOCHI LIU, HONG-HAI DAI
  • Patent number: 8648968
    Abstract: A saturation adjusting apparatus for processing a pixel, which has three color components each having a value falling within a range defined by upper and lower extreme values, of a RGB color model includes an extreme value controller and a component adjuster. The extreme value controller determines maximum and minimum extreme value thresholds for ensuring that the values of the color components of the pixel after undergoing linear color correction processing based on a correction indicator fall within the range defined by the upper and lower extreme values. The component adjuster includes a decision-making unit for choosing the correction indicator from a group of values which includes the maximum extreme value threshold, the minimum extreme value threshold, and a saturation setting. The component adjuster further includes a color corrector for performing linear color correction processing on the three color components of the pixel using the correction indicator.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: February 11, 2014
    Assignee: Realtek Semiconductor Corp.
    Inventors: Li-Cong Hou, Dong-Yu He, Hong-Hai Dai
  • Patent number: 8327230
    Abstract: A data structure for a flash memory and data reading/writing method thereof are disclosed. A 512 bytes data and a redundant code derived from the data encoded with a 6-bit error correcting code scheme are stored in a first sector and a second sector with sequential address in a block of the flash memory respectively. A logic block address information of this block is divided into two parts that are stored in the first sector and the second sector respectively.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: December 4, 2012
    Assignee: Realtek Semiconductor Corp.
    Inventors: Jian-Qiang Ni, Dong-Yu He, Chun-Ting Liao
  • Publication number: 20120110419
    Abstract: A data structure for a flash memory and data reading/writing method thereof are disclosed. A 512 bytes data and a redundant code derived from the data encoded with a 6-bit error correcting code scheme are stored in a first sector and a second sector with sequential address in a block of the flash memory respectively. A logic block address information of this block is divided into two parts that are stored in the first sector and the second sector respectively.
    Type: Application
    Filed: January 6, 2012
    Publication date: May 3, 2012
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventors: Jian-Qiang Ni, Dong-Yu He, Chun-Ting Liao
  • Patent number: 8122303
    Abstract: A data structure for a flash memory and data reading/writing method thereof are disclosed. A 512 bytes data and a redundant code derived from the data encoded with a 6-bit error correcting code scheme are stored in a first sector and a second sector with sequential address in a block of the flash memory respectively. A logic block address information of this block is divided into two parts that are stored in the first sector and the second sector respectively.
    Type: Grant
    Filed: May 19, 2008
    Date of Patent: February 21, 2012
    Assignee: Realtek Semiconductor Corp.
    Inventors: Jian-Qiang Ni, Dong-Yu He, Chun-Ting Liao
  • Publication number: 20120026404
    Abstract: A saturation adjusting apparatus for processing a pixel, which has three color components each having a value falling within a range defined by upper and lower extreme values, of a RGB color model includes an extreme value controller and a component adjuster. The extreme value controller determines maximum and minimum extreme value thresholds for ensuring that the values of the color components of the pixel after undergoing linear color correction processing based on a correction indicator fall within the range defined by the upper and lower extreme values. The component adjuster includes a decision-making unit for choosing the correction indicator from a group of values which includes the maximum extreme value threshold, the minimum extreme value threshold, and a saturation setting. The component adjuster further includes a color corrector for performing linear color correction processing on the three color components of the pixel using the correction indicator.
    Type: Application
    Filed: July 29, 2011
    Publication date: February 2, 2012
    Applicant: Realtek Semiconductor Corp.
    Inventors: Li-Cong HOU, Dong-Yu HE, Hong-Hai DAI
  • Patent number: 8055983
    Abstract: A data writing method for flash memory and an error correction encoding/decoding method thereof are disclosed. In an embodiment of the data writing method, a 6-bit ECC scheme using a Reed-Solomon code derived from a Galois Field GF (29) is used to encode a data for generating a redundant which requires smaller storing space. In an embodiment of the error correction encoding/decoding method, an erase checking value corresponding to the status where all the bytes of data area and parameter storing area are “0xff” is provided to improve the security of stored data.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: November 8, 2011
    Assignee: Realtek Semiconductor Corp.
    Inventors: Jian Qiang Ni, Dong Yu He, Chun Ting Liao
  • Publication number: 20080294965
    Abstract: A data writing method for flash memory and an error correction encoding/decoding method thereof are disclosed. In an embodiment of the data writing method, a 6-bit ECC scheme using a Reed-Solomon code derived from a Galois Field GF (29) is used to encode a data for generating a redundant which requires smaller storing space. In an embodiment of the error correction encoding/decoding method, an erase checking value corresponding to the status where all the bytes of data area and parameter storing area are “0xff” is provided to improve the security of stored data.
    Type: Application
    Filed: May 23, 2008
    Publication date: November 27, 2008
    Applicant: Realtek Semiconductor Corp.
    Inventors: Jian-Qiang Ni, Dong-Yu He, Chun-Ting Liao
  • Publication number: 20080294935
    Abstract: A data structure for a flash memory and data reading/writing method thereof are disclosed. A 512 bytes data and a redundant code derived from the data encoded with a 6-bit error correcting code scheme are stored in a first sector and a second sector with sequential address in a block of the flash memory respectively. A logic block address information of this block is divided into two parts that are stored in the first sector and the second sector respectively.
    Type: Application
    Filed: May 19, 2008
    Publication date: November 27, 2008
    Inventors: Jian-Qiang NI, Dong-Yu He, Chun-Ting Liao
  • Publication number: 20080147966
    Abstract: The present invention discloses a flash memory device, an update method and program search method thereof. The flash memory device includes a read-only memory unit, a flash memory unit and a control unit. The read-only memory unit is used to store a first program code. The flash memory unit is used to store a second program code and digital data. The control unit coupled to the flash memory unit and the read-only memory unit is used to control the operation of the flash memory unit based on the first program code and the second program code. Hence, the upgrade time for the flash memory device can be shortened and the manufacture cost can be reduced.
    Type: Application
    Filed: December 18, 2007
    Publication date: June 19, 2008
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventors: Chun-Ting Liao, Dong-Yu He, Guang-Huan Zhao