Patents by Inventor Dong Yun Jung

Dong Yun Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220153030
    Abstract: The present invention provides an apparatus for treating a substrate, the apparatus including: a head unit including a head formed with one or more nozzles that discharge a treatment liquid to a substrate; and a head maintenance unit configured to perform maintenance for the head, in which the head maintenance unit may include: a liquid receiving block formed with one or more liquid receiving parts having liquid receiving spaces with open tops; a decompression line fluidly-communicating with the liquid receiving space and configured to provide reduced pressure to the liquid receiving space; and a decompression valve installed in the decompression line.
    Type: Application
    Filed: November 18, 2021
    Publication date: May 19, 2022
    Inventors: Byung Joo LEE, Sang Hwa LEE, Dong Yun LEE, Jee Yong JUNG, Hahn Seok JEON, Kang KWON, Jae Hun JEONG, Sang Hoon KIM
  • Publication number: 20220020671
    Abstract: The present invention minimizes parasitic inductance at the time of packaging a semiconductor that requires high efficiency and high-speed switching driving. In implementing a semiconductor package composed of one or more switching devices and one or more diode devices, the present invention provides a flip-stack structure in which a switching device is mounted on an insulating substrate or a metal frame, a flat metal is bonded onto the switching device, and a diode device is flipped and stacked on the flat metal, and accordingly, the flat metal with a large area is used for connection between the devices and between the devices and the insulating substrate, thereby minimizing parasitic inductance generated at a time of semiconductor packaging and automating the entire process of the semiconductor packaging.
    Type: Application
    Filed: July 20, 2021
    Publication date: January 20, 2022
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Dong Yun JUNG, Hyun Gyu JANG, Sung Kyu KWON, Kun Sik PARK, Jong Il WON, Seong Hyun LEE, Jong Won LIM, Doo Hyung CHO
  • Publication number: 20210408265
    Abstract: The present invention forms an off-FET channel having a uniform and short length by using a self-align process of a method of forming and recessing a spacer, thereby enhancing the current driving capability of an off-FET and the uniformity of a device operation.
    Type: Application
    Filed: June 23, 2021
    Publication date: December 30, 2021
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Kun Sik PARK, Jong Il WON, Doo Hyung CHO, Hyun Gyu JANG, Dong Yun JUNG
  • Publication number: 20210335681
    Abstract: A ceramic stacked semiconductor package and a method of packaging a ceramic stacked semiconductor is disclosed. Inner walls of junctions are formed between ceramic layers and a molding resin to have a non-uniform boundary shape (e.g., Z shape, an uneven shape, a zigzag shape, etc.) so that bonding areas and lengths of the molding resin and the ceramic layers are increased, and thus adhesion is improved and movement paths of moisture are increased, thereby improving anti-humidity property and reliability of the semiconductor package. Further, by arranging via-holes at different positions for each layer so as not to overlap each other between the layers, movement paths of moisture passing through the via-holes are increased, and thus the anti-humidity property and reliability of the stacked package are additionally improved.
    Type: Application
    Filed: March 30, 2021
    Publication date: October 28, 2021
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Hyun Gyu JANG, Dong Yun JUNG, Doo Hyung CHO, Kun Sik PARK, Jong Won LIM
  • Patent number: 10848074
    Abstract: Provided is a high voltage bridge rectifier. The high voltage bridge rectifier includes a supporter, a substrate on the supporter, a plurality of equivalent diode circuits mounted on the substrate, interconnection lines, and terminals. The substrate may include an insulation layer, element pads disposed on a center of the insulation layer, and terminal pads disposed on an edge of the insulation layer to surround the element pads.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: November 24, 2020
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Chi Hoon Jun, Sang Choon Ko, Dong Yun Jung, Jong-Moon Park, Hyun-Gyu Jang
  • Patent number: 10734878
    Abstract: The present disclosure relates to a spherical wheel motor and a control system thereof, and more particularly, the spherical wheel motor and the control system include a spherical rotor and a stator surrounding an upper surface of the rotor. The rotor includes a spherical outer shell part, a first axial magnet extending in a horizontal direction in the outer shell part, a second axial magnet extending in the horizontal direction and facing the first axial magnet, and a rotary magnet belt provided in a form of a belt with the first axial magnet and the second axial magnet as a central axis. The rotary magnet belt includes a plurality of first rotary magnets and a plurality of second rotary magnets arranged alternately.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: August 4, 2020
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Minki Kim, Junbo Park, Dong Yun Jung
  • Publication number: 20200119654
    Abstract: Provided is a high voltage bridge rectifier. The high voltage bridge rectifier includes a supporter, a substrate on the supporter, a plurality of equivalent diode circuits mounted on the substrate, interconnection lines, and terminals. The substrate may include an insulation layer, element pads disposed on a center of the insulation layer, and terminal pads disposed on an edge of the insulation layer to surround the element pads.
    Type: Application
    Filed: September 11, 2019
    Publication date: April 16, 2020
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Chi Hoon JUN, Sang Choon KO, Dong Yun JUNG, Jong-Moon PARK, Hyun-Gyu JANG
  • Patent number: 10381736
    Abstract: The present disclosure relates to a pre-5th-generation (5G) or 5G communication system to be provided for supporting higher data rates beyond 4th-generation (4G) communication system such as long term evolution (LTE). An electronic device is provided in a wireless communication system. The device comprises a plurality of antenna sets; a plurality of antenna elements configuring the plurality of antenna sets; an RF transceiver including a plurality of switches for selecting the plurality of antenna elements and a plurality of phase shifters for shifting the phase of a signal transmitted/received through the plurality of antenna elements; and a control unit for determining a beam forming direction and the phase of the signal by simultaneously controlling the plurality of switches and the plurality of phase shifters according to a beambook.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: August 13, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Yun Jung, Sung-Tae Choi, Ji-Hoon Kim, Yi-Ju Roh, Yun-A Shim, Dong-Hyun Lee, Seung-Pyo Hong
  • Publication number: 20190097513
    Abstract: The present disclosure relates to a spherical wheel motor and a control system thereof, and more particularly, the spherical wheel motor and the control system include a spherical rotor and a stator surrounding an upper surface of the rotor. The rotor includes a spherical outer shell part, a first axial magnet extending in a horizontal direction in the outer shell part, a second axial magnet extending in the horizontal direction and facing the first axial magnet, and a rotary magnet belt provided in a form of a belt with the first axial magnet and the second axial magnet as a central axis. The rotary magnet belt includes a plurality of first rotary magnets and a plurality of second rotary magnets arranged alternately.
    Type: Application
    Filed: September 5, 2018
    Publication date: March 28, 2019
    Inventors: Minki KIM, Junbo PARK, Dong Yun JUNG
  • Patent number: 10014401
    Abstract: A semiconductor device includes a semiconductor structure including a substrate, a first semiconductor layer on the substrate, and a second semiconductor layer on the first semiconductor layer, a first passivation pattern provided on the semiconductor structure, and first and second conductive patterns provided on the semiconductor structure and spaced from the first passivation pattern.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: July 3, 2018
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jeho Na, Hyung Seok Lee, Chi Hoon Jun, Sang Choon Ko, Myungjoon Kwack, Young Rak Park, Woojin Chang, Hyun-Gyu Jang, Dong Yun Jung
  • Patent number: 9948484
    Abstract: The present invention relates to a method and an apparatus for direct current offset calibration of a direct conversion receiver, a Direct Current (DC) offset calibration apparatus of a direct conversion receiver includes a plurality of variable gain amplifiers for amplifying an input signal based on a gain control value, a DC offset monitoring unit for monitoring a DC offset for an output signal of the plurality of variable gain amplifiers, a plurality of variable Digital to Analog Converters (DACs) for controlling a current applied to each of the plurality of variable gain amplifiers according to a current control code, and a DC offset cancellation unit for determining a current control code set which minimizes the DC offset value per preset gain control value, and thus the DC offset can be precisely cancelled without being affected by external factors such as a signal modulation method and heat and performance degradation of the receiver can be prevented.
    Type: Grant
    Filed: January 2, 2015
    Date of Patent: April 17, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yi-Ju Roh, Ji-Hoon Kim, Ju-Ho Son, Yun-A Shim, Dong-Hyun Lee, Dong-Yun Jung, Sung-Tae Choi, Seung-Pyo Hong
  • Patent number: 9905654
    Abstract: Provided is a bridge diode according to an embodiment of the inventive concept. The bridge diode includes a first structure including a first lower nitride film and a first upper nitride film, which are laminated on the substrate, a second structure including a second lower nitride film and a second upper nitride film, which are laminated on the substrate, a first electrode structural body disposed on the first structure, and a second electrode structural body disposed on the second structure.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: February 27, 2018
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Dong Yun Jung, Hyun Soo Lee, Sang Choon Ko, Minki Kim, Jeho Na, Eun Soo Nam, Young Rak Park, Junbo Park, Hyung Seok Lee, Hyun-Gyu Jang, Chi Hoon Jun
  • Patent number: 9800181
    Abstract: Provided is a hybrid diode device. The hybrid diode device includes a first lower nitride layer disposed on a substrate and including a first 2-dimensional electron gas (2DEG) layer, a second lower nitride layer extending from the first lower nitride layer to the outside of the substrate and including a second 2DEG layer, a first upper nitride layer disposed on the first lower nitride layer, a second upper nitride layer disposed on the second lower nitride layer, a first cap layer disposed on the first upper nitride layer, a second cap layer disposed on the second upper nitride layer, a first electrode structure connected to the first lower nitride layer and the first cap layer; and a second electrode structure connected to the second lower nitride layer and the first electrode structure. The second lower nitride layer generates electric energy through dynamic movement.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: October 24, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Chi Hoon Jun, Sang Choon Ko, Minki Kim, Jeho Na, Young Rak Park, Junbo Park, Hyun Soo Lee, Hyung Seok Lee, Hyun-Gyu Jang, Dong Yun Jung
  • Patent number: 9755027
    Abstract: Provided is an electronic device. The electronic device includes a first semiconductor layer and a second semiconductor layer sequentially stacked on a substrate and a source electrode, a gate electrode, and a drain electrode arranged on the second semiconductor layer. The electronic device further includes a field plate which is electrically connected to the source electrode and extends towards the drain electrode, wherein the field plate becomes farther away from the substrate as the field plate becomes closer to the drain electrode.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: September 5, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Hyung Seok Lee, Ki Hwan Kim, Sang Choon Ko, Zin-Sig Kim, Jeho Na, Eun Soo Nam, Young Rak Park, Junbo Park, Chi hoon Jun, Dong Yun Jung
  • Patent number: 9748941
    Abstract: Provided is a stabilizing circuit structure using a sense field effect transistor (sense-FET). A power semiconductor module includes a depletion-mode field effect transistor (D-mode FET) and the sense FET that has same structure as the D-mode FET and varies in area. Also the power semiconductor module includes not only an enhancement-mode field effect transistor (E-mode FET), but also the stabilizing circuit including circuit elements such as a resistor, a capacitor, an inductor, or a diode.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: August 29, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Minki Kim, Hyun-Gyu Jang, Dong Yun Jung, Sang Choon Ko, Hyun Soo Lee, Chi Hoon Jun
  • Publication number: 20170213904
    Abstract: A semiconductor device includes a semiconductor structure including a substrate, a first semiconductor layer on the substrate, and a second semiconductor layer on the first semiconductor layer, a first passivation pattern provided on the semiconductor structure, and first and second conductive patterns provided on the semiconductor structure and spaced from the first passivation pattern.
    Type: Application
    Filed: January 24, 2017
    Publication date: July 27, 2017
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Jeho NA, Hyung Seok LEE, Chi Hoon JUN, Sang Choon KO, Myungjoon KWACK, Young Rak PARK, Woojin CHANG, Hyun-Gyu JANG, Dong Yun JUNG
  • Publication number: 20170141704
    Abstract: Provided is a hybrid diode device. The hybrid diode device includes a first lower nitride layer disposed on a substrate and including a first 2-dimensional electron gas (2DEG) layer, a second lower nitride layer extending from the first lower nitride layer to the outside of the substrate and including a second 2DEG layer, a first upper nitride layer disposed on the first lower nitride layer, a second upper nitride layer disposed on the second lower nitride layer, a first cap layer disposed on the first upper nitride layer, a second cap layer disposed on the second upper nitride layer, a first electrode structure connected to the first lower nitride layer and the first cap layer; and a second electrode structure connected to the second lower nitride layer and the first electrode structure. The second lower nitride layer generates electric energy through dynamic movement.
    Type: Application
    Filed: October 21, 2016
    Publication date: May 18, 2017
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Chi Hoon JUN, Sang Choon KO, Minki KIM, Jeho NA, Young Rak PARK, Junbo PARK, Hyun Soo LEE, Hyung Seok LEE, Hyun-Gyu JANG, Dong Yun JUNG
  • Publication number: 20170117889
    Abstract: Provided is a stabilizing circuit structure using a sense field effect transistor (sense-FET). A power semiconductor module includes a depletion-mode field effect transistor (D-mode FET) and the sense FET that has same structure as the D-mode FET and varies in area. Also the power semiconductor module includes not only an enhancement-mode field effect transistor (E-mode FET), but also the stabilizing circuit including circuit elements such as a resistor, a capacitor, an inductor, or a diode.
    Type: Application
    Filed: July 29, 2016
    Publication date: April 27, 2017
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Minki KIM, Hyun-Gyu JANG, Dong Yun JUNG, Sang Choon KO, Hyun Soo LEE, Chi Hoon JUN
  • Patent number: 9613884
    Abstract: Provided is a semiconductor device. The semiconductor device includes a substrate including a cantilever configured to generate a flow of cooling media through dynamic movement, an active area on the substrate which an electronic device is provided on, an insulation layer disposed to be spaced apart from the active area on the substrate, a lower electrode on the insulation layer, a piezoelectric film on the lower electrode, and an upper electrode on the piezoelectric film.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: April 4, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Chi Hoon Jun, Jeho Na, Dong Yun Jung, Sang Choon Ko, Eun Soo Nam, Hyung Seok Lee
  • Publication number: 20170077282
    Abstract: Provided is an electronic device. The electronic device includes a first semiconductor layer and a second semiconductor layer sequentially stacked on a substrate and a source electrode, a gate electrode, and a drain electrode arranged on the second semiconductor layer. The electronic device further includes a field plate which is electrically connected to the source electrode and extends towards the drain electrode, wherein the field plate becomes farther away from the substrate as the field plate becomes closer to the drain electrode.
    Type: Application
    Filed: September 14, 2016
    Publication date: March 16, 2017
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Hyung Seok LEE, Ki Hwan KIM, Sang Choon KO, Zin-Sig KIM, Jeho NA, EUN SOO NAM, Young Rak PARK, Junbo PARK, Chi Hoon JUN, Dong Yun JUNG