Abstract: A method for processing a heat exchanger includes: preparing a plurality of heat exchange tube semi-finished products, each heat exchange tube semi-finished product including a first wall and a second wall arranged in a thickness direction of the heat exchange tube semi-finished product, and the second wall having a first gap penetrating the second wall in the thickness direction; arranging N heat exchange tube semi-finished products spaced apart by a predetermined distance in a first direction, N>4, the thickness direction of the heat exchange tube semi-finished product being parallel or angled to the first direction, and in the first direction, the arranged heat exchange tube semi-finished products being sequentially defined as a first tube, a second tube, . . . , a N?1th tube, and a Nth tube; placing the second wall of the first tube towards the second tube; and placing the second wall of the Nth tube towards the N?1th tube.

Abstract: In an approach, a processor performs document layout analysis on a document generating a plurality of textual regions; extracts characteristics from each of the plurality of textual regions and associates the respective characteristics to the respective textual region as metadata; classifies each of the plurality of textual regions as an optical character recognition (OCR) region, non-OCR valuable region, or non-OCR non-valuable region using a classifier; performs OCR on each OCR region generating an OCR output; identifies associated constant OCR data from a constant OCR data repository for each non-OCR valuable region; merges the associated constant OCR data with the OCR output generating a complete OCR data for the received document; performs data extraction on the complete OCR data to identify data fields and key-value pairs generating extracted data; and determines whether the extracted data is valid based on a set of rules.

Abstract: This application provides an optical module, an electronic device, a communication system, and a related processing method. The optical module includes: a first processing unit, and a sampling unit, a sampled information storage unit, and a fault information storage unit that are separately electrically connected to the first processing unit. The sampling unit is configured to collect first sampled parameters, and store the first sampled parameters in the sampled information storage unit by using the first processing unit. The first processing unit is configured to: when identifying alarm information, read the first sampled parameters in the sampled information storage unit, determine, based on the first sampled parameters, fault type information corresponding to the alarm information, and store the fault type information in the fault information storage unit. The optical module does not need to transmit a large amount of sampled data to the electronic device.

Abstract: A fracturing apparatus includes a motor, a first plunger pump, a power supply platform, a gas turbine engine, a generator, and one or more rectifiers. At least two of the gas turbine engine, the generator, and the one or more rectifiers are arranged on the power supply platform. A first end of the generator is connected to the gas turbine engine. A second end of the generator is connected to the one or more rectifiers. The generator is configured to output a voltage to the one or more rectifiers. The one or more rectifiers are configured to provide power to the motor. The motor is configured to drive the first plunger pump.

Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) coupled to first one or more inductors, the first VR is to provide power to a first power domain; and a second VR coupled to second one or more inductors at least one of which is inductively coupled to at least one of the first one or more inductors, the second VR is to provide power to a second power domain separate from the first power domain, wherein there is a non-zero phase angle offset between switching transistors of the first VR relative to the second VR.

Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) coupled to first one or more inductors, the first VR is to provide power to a first power domain; and a second VR coupled to second one or more inductors at least one of which is inductively coupled to at least one of the first one or more inductors, the second VR is to provide power to a second power domain separate from the first power domain, wherein there is a non-zero phase angle offset between switching transistors of the first VR relative to the second VR.

Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) coupled to first one or more inductors, the first VR is to provide power to a first power domain; and a second VR coupled to second one or more inductors at least one of which is inductively coupled to at least one of the first one or more inductors, the second VR is to provide power to a second power domain separate from the first power domain, wherein there is a non-zero phase angle offset between switching transistors of the first VR relative to the second VR.

Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) coupled to first one or more inductors, the first VR is to provide power to a first power domain; and a second VR coupled to second one or more inductors at least one of which is inductively coupled to at least one of the first one or more inductors, the second VR is to provide power to a second power domain separate from the first power domain, wherein there is a non-zero phase angle offset between switching transistors of the first VR relative to the second VR.

Abstract: A power plane including a supply power pin receptacle, a first connector power pin receptacle, and a second power pin receptacle, where a first electrical resistance between the supply power pin receptacle and the first connector power pin receptacle is substantially equal to a second electrical resistance between the supply power pin receptacle and the second connector power pin receptacle.

Abstract: Trace configurations for carrying high-speed digital differential signals provide for reduced conduction loss and improved signal integrity. In one embodiment, a circuit board has a first set of conductive traces disposed on non-conductive material, and a second set of conductive traces parallel to the first set and disposed within the conductive material. The second set is separated from the first set by non-conductive material. Corresponding traces of the first and second sets may be in a stacked configuration. In other embodiments, conductive material may be provided between corresponding traces of the first and second sets resulting in an “I-shaped” or “U-shaped” cross-section. In yet other embodiments, the trace configurations have “T-shaped” and “L-shaped” cross-sections.

Abstract: Disclosed is an electronic device 100 with a housing for electronic circuitry (110) and a flexible sheet (102) that completely covers both a touch screen region (114) and a keypad region (112) of the electronic device (100). The flexible sheet (102) is mounted to the housing and provides a front face of the electronic device (100).

Abstract: In an integrated circuit design, flex tape is used to provide signal ingress/egress to/from the integrated circuit design. Various architectures for the signal ingress/egress via flex tape is provided. In one embodiment, coaxial design is provided. In another embodiment, a coplanar waveguide design is provided.

Abstract: A power plane including a supply power pin receptacle, a first connector power pin receptacle, and a second power pin receptacle, where a first electrical resistance between the supply power pin receptacle and the first connector power pin receptacle is substantially equal to a second electrical resistance between the supply power pin receptacle and the second connector power pin receptacle.

Abstract: According to some embodiments, a system includes an integrated circuit package to support an integrated circuit die. The integrated circuit package may include a plurality of conductive contacts and a decoupling capacitor. The decoupling capacitor may include a positive terminal contact pad coupled to a first one of the plurality of conductive contacts, the positive terminal contact pad comprising a first substantially non-conductive area, and a negative terminal contact pad coupled to a second one of the plurality of conductive contacts, the negative terminal contact pad comprising a second substantially non-conductive area.

Abstract: According to some embodiments, a system includes an integrated circuit package to support an integrated circuit die. The integrated circuit package may include a plurality of conductive contacts, and an element having a plurality of resistive portions, each of the plurality of resistive portions being coupled to a respective one of the plurality of conductive contacts. The integrated circuit package may further include a decoupling capacitor having a plurality of capacitor pads, each of the plurality of capacitor pads being coupled to a respective one of the plurality of resistive portions.

Abstract: According to some embodiments, a device includes a first conductive plane electrically coupled to a first terminal associated with a first polarity and a second terminal associated with the first polarity, a second conductive plane electrically coupled to a third terminal associated with a second polarity, a dielectric disposed between the first conductive plane and the second conductive plane, a third conductive plane electrically coupled to the second terminal and not electrically coupled to the first terminal, and a second dielectric disposed between the second conductive plane and the third conductive plane. A first capacitance is present between the first terminal and the third terminal, a second capacitance is present between the second terminal and the third terminal, and the first capacitance and the second capacitance may be substantially dissimilar.

Abstract: According to some embodiments, a capacitor includes a first external capacitor plane including a first at least one terminal of a first polarity, and a first internal capacitor plane including a second at least one terminal of the first polarity. The second at least one terminal of the first polarity may be electrically coupled to the first at least one terminal of the first polarity, and a total area of the second at least one terminal of the first polarity may be less than a total area of the first at least one terminal of the first polarity.

Abstract: An improved silicon building block is disclosed. In an embodiment, the silicon building block has at least two vias through it. The silicon building block is doped and the vias filled with a first material, and, optionally, selected ones of the vias filled instead with a second material. In an alternative embodiment, regions of the silicon building block have metal deposited on them.

Abstract: DPN (decoupled plasma nitridation) is used to improve robustness of ultra thin gate oxides. Conventionally, this is followed by an anneal in pure helium to remove structural defects in the oxide. However, annealing under these conditions has been found to cause a deterioration of the electrical performance of devices. This problem has been overcome by annealing, in a 1:4 oxygen-nitrogen mixture (1,050° C. at about 10 torr) instead of in helium or nitrogen oxide. This results in a gate oxide that is resistant to boron contamination without suffering any loss in its electrical properties.

Abstract: An inter-digital capacitor may be used in a power socket for a microelectronic device. In one embodiment an integrated, low-resistance power and ground terminal configuration is disclosed. The capacitor plates are alternatively coupled to the power and ground terminals. Two polarity types are disclosed. A method of operation is also described.