Abstract: A configuration control circuit (400) allows a PLD to be quickly re-configured to implement different functions without requiring any configuration memory cells. The control circuit (400) includes a first input (IN1) connected to a first hardwired configuration bit (HCB1), a second input (IN2) connected to a second hardwired configuration bit (HCB2), an output (OUT) connected to one or more of the PLD's configurable elements (110), and a select circuit (402) to selectively connect either the first input (IN1) or the second input (IN2) to the output (OUT) in response to a select signal (SEL).

Abstract: A method of fabricating a nanostructured solid oxide fuel cell includes dispersing ceria and doped ceria nanoparticles in a first colloidal solution, atomizing the first colloidal solution into a spray, depositing the spray onto a substrate to form a thin film electrolyte, dispersing a nanocomposite powder including ceria and CuO in the first solution, forming a second colloidal solution, atomizing the second colloidal solution into a second spray, and depositing the second spray over the thin film electrolyte as an interfacial layer.

Abstract: An input circuit includes a first buffer having a first power terminal coupled to a first supply voltage, a second power terminal coupled to ground potential, an input to receive an input signal, and an output to generate a first output signal, a second buffer having a first terminal coupled to a second supply voltage, a second terminal coupled to a bias node, an input to receive the input signal, and an output to generate a second output signal, and a control circuit configured to selectively connect the bias node either to the second supply voltage or to ground potential in response to an enable signal.

Abstract: A clock selection circuit includes an output multiplexer, control logic, and edge detection logic. The multiplexer includes inputs to receive multiple input clock signals, an output to generate the output clock signal, and a control terminal to receive a synchronized clock select signal. The control logic includes a first input to receive a clock select signal, a second input to receive a first control clock signal, a third input to receive a synchronization signal, and an output to selectively update the synchronized clock select signal with transitions in the clock select signal. The edge detection logic includes first inputs to receive the multiple input clock signals, a second input to receive a second control clock signal, and an output to generate the synchronization signal.

Abstract: A complex programmable logic device (CPLD) that can be scaled upwards in size without unacceptable increases in die size or signal delays. A CPLD includes a two-dimensional array including rows and columns of function blocks and input/output (I/O) blocks programmably interconnected by a de-centralized interconnect structure. The interconnect structure includes numbers of interconnect lines segmented into shorter lengths. Programmable multiplexer circuits couple the segmented interconnect lines to the function blocks and I/O blocks. Programmable switch matrices couple the segmented interconnect lines together into longer interconnect lines of the desired length.

Abstract: A method of fabricating a nanostructured solid oxide fuel cell includes dispersing ceria and doped ceria nanoparticles in a first colloidal solution, atomizing the first colloidal solution into a spray, depositing the spray onto a substrate to form a thin film electrolyte, dispersing a nanocomposite powder including ceria and CuO in the first solution, forming a second colloidal solution, atomizing the second colloidal solution into a second spray, and depositing the second spray over the thin film electrolyte as an interfacial layer.

Abstract: The invention comprises novel undoped and doped nanometer-scale CeO2 particles as well as a novel semi-batch reactor method for directly synthesizing the novel particles at room temperature. The powders exhibited a surface area of approximately 170 m2/g with a particle size of about 3-5 nm, and are formed of single crystal particles that are of uniform size and shape. The particles' surface area could be decreased down to 5 m2/g, which corresponds to a particle size of 100 nm, by thermal annealing at temperatures up to 1000° C. Control over the particle size, size distribution and state of agglomeration could be achieved through variation of the mixing conditions such as the feeding method, stirrer rate, amount of O2 gas that is bubbled through the reactor, the temperature the reaction is carried out at, as well as heating the final product at temperatures ranging from 150° to 1000° C.

Abstract: Pseudo-differential multiplexer circuits and methods. The circuit input signals are provided to two similar multiplexers, one of which is driven by true signals and one by the complementary input signals. No matter what the values of the circuit input signals, at least one of the two multiplexers always selects a low value. Therefore, at least one of the two multiplexers has the capability of overcoming a value stored in an output circuit (e.g., a latch) coupled to the output terminals of the two multiplexers. Thus, even when neither multiplexer can provide a high signal at the full value of power high VDD, the output circuit provides the correct output value. The invention also encompasses methods of selecting between circuit input signals by utilizing a pseudo-differential multiplexing technique, e.g., utilizing multiplexer circuits similar to those described above.

Abstract: An antenna includes a ground plate, a conductive branch having a conductor feed extended for electrically coupling to the ground plate, and a cable electrically coupled to the conductor feed for signal transmitting and receiving purpose. The conductive branch is inclined relative to the conductor feed and the ground plate, for increasing signal transmitting and receiving directions and frequency range for the antenna, and for avoiding dead angles for the antenna. One or more conductor extensions may be electrically coupled between the conductor feed and the ground plate, for increase a signal transmitting and receiving or communicating path between the conductive branch and the ground plate.

Abstract: The invention comprises novel undoped and doped nanometer-scale CeO2 particles as well as a novel semi-batch reactor method for directly synthesizing the novel particles at room temperature. The powders exhibited a surface area of approximately 170 m2/g with a particle size of about 3–5 nm, and are formed of single crystal particles that are of uniform size and shape. The particles' surface area could be decreased down to 5 m2/g, which corresponds to a particle size of 100 nm, by thermal annealing at temperatures up to 1000° C. Control over the particle size, size distribution and state of agglomeration could be achieved through variation of the mixing conditions such as the feeding method, stirrer rate, amount of O2 gas that is bubbled through the reactor, the temperature the reaction is carried out at, as well as heating the final product at temperatures ranging from 150° to 1000° C.

Abstract: Compounds and compositions of the following formula: and analogs and stereoisomers thereof (and pharmaceutically acceptable carriers). Additionally disclosed is a method of inhibiting hypoxia-inducible factor-1 function in a patient or sample thereof, comprising administering to the patient or sample an effective inhibiting amount of a compound or composition of the present invention.

Abstract: Pseudo-differential multiplexer circuits and methods. The circuit input signals are provided to two similar multiplexers, one of which is driven by true signals and one by the complementary input signals. No matter what the values of the circuit input signals, at least one of the two multiplexers always selects a low value. Therefore, at least one of the two multiplexers has the capability of overcoming a value stored in an output circuit (e.g., a latch) coupled to the output terminals of the two multiplexers. Thus, even when neither multiplexer can provide a high signal at the full value of power high VDD, the output circuit provides the correct output value. The invention also encompasses methods of selecting between circuit input signals by utilizing a pseudo-differential multiplexing technique, e.g., utilizing multiplexer circuits similar to those described above.

Abstract: A selectively enabled clamp circuit for limiting voltage overshoot on an input/output (I/O) pin of an associated integrated circuit (IC) device includes a single discharge transistor and a select circuit. The single discharge transistor is connected between the I/O pin and ground potential, and the select circuit is coupled to the I/O pin and includes an input to receive an enable signal and an output coupled to a gate of the signal discharge transistor. For some embodiments, the select circuit includes a level shifter circuit and a voltage detection circuit.

Abstract: A technique and circuit implementation are described for automatically detecting a change in a power supply voltage and selectively reconfiguring a circuit for optimized performance at the changed voltage. One application of particular interest is an auto-detect level shifter. The auto-detect level shifter can be used in an output driver and can be automatically enabled if it is needed to optimize performance for various I/O standards, including those that operate at different voltages.

Abstract: A method and apparatus for adaptive replication of code units is described. In one embodiment, the method comprises gathering run-time capability and preference information for an application, client device and server regarding an application service object; and directing replication of at least one application service object from the server to the client device based on the client, the server, and the application run-time capability and preference information.

Abstract: Schema-driven XML parsing techniques allow an XML parser to optimize its parsing process by composing parse and to dynamically generate parsing code components based on XML schema definition for the targeted XML document. These techniques reduce the XML parsing time and reduce the memory requirement during parsing process. Further, a reconfigurable parser is provided which is guided during parsing of the XML document by XML element lexicographical information and state transition information extracted from a schema associated with the XML document. Pre-allocated element object pools may be provided based on the schema analysis to reduce the requirements for dynamic memory allocation and de-allocation operations.

Abstract: Compounds and compositions that effectively block hypoxia-inducible factor-1 function, and methods of use thereof. The compounds and compositions of the present invention are useful in the prevention and treatment of cancer, stroke, heart disease, ocular neovascular diseases, and arthritis.

Abstract: An integrated clock doubler and polarity control circuit are described. The circuit provides high speed response between an input signal and an output signal, achieving clock doubling by passing the input signal through a delay circuit and using the output of the delay circuit to select between two paths for inverting or not inverting the input signal to produce the output signal. In one embodiment, the inverting path is a CMOS inverter with input terminal receiving the input signal, output terminal providing the output signal, and power terminals controlled by the delay circuit.

Abstract: Delay lock loop (DLL) circuits, systems, and methods providing glitch-free output clock signals. Glitches are eliminated from an output clock signal by using shift registers including a single token bit to select one of many delayed clock signals. A DLL clock multiplexer includes a series of shift registers, each of which selects only one of the many input clock signals at each stage. Thus, only one clock signal is selected at any given time. Delay is added or subtracted from the loop by shifting the token bit within each shift register. The token bit is shifted by a single position at a time. Therefore, no glitching occurs.