Abstract: Methods and systems for fabricating an integrated circuit include training a machine learning model using a training set that includes known physical design layout patterns that are classified according to whether the patterns include a hotspot. It is determined whether an input physical design layout pattern includes a hotspot using the machine learning model. A hotspot localization is generated for the input physical design layout patterns. The input physical design pattern is adjusted to cure the hotspot. A circuit is fabricated in accordance with the adjusted input physical design layout pattern.

Abstract: A method is presented for incorporating skip vias in a place and route flow of an integrated circuit design. The method includes employing a place and route tool to add the skip vias, each skip via extending through a metallization layer to electrically connect a metal layer above the metallization layer to a metal layer below the metallization layer and, when a violation of a design rule is detected due to the addition of one or more of the skip vias, substituting skip vias that violate the design rule with a standard via.

Abstract: In accordance with an embodiment of the present invention, a photolithographic mask is provided. The photolithographic mask includes at least one merged via pattern in the photolithographic mask for printing a merged via opening in a resist layer, wherein the at least one merged via pattern includes a compound shape having a first rectangular opening portion and a second rectangular opening portion that intersect at an angle.

Abstract: A method for manufacturing a semiconductor device includes forming a first field-effect transistor (FET) on a substrate, the first FET comprising a first plurality of channel regions extending in a first direction, and stacking a second FET on the first FET, the second FET comprising a second plurality of channel regions extending in a second direction perpendicular to the first direction, wherein the first FET comprises a first gate region extending in the second direction across the first plurality of channel regions, and the second FET comprises a second gate region extending in the first direction across the second plurality of channel regions.

Abstract: A system and method to perform risk assessment or design rule determination for an integrated circuit involves generating two or more process variation contours based on corresponding two or more combinations of two or more factors that affect manufacturability of the integrated circuit. Each of the two or more process variation contours is associated with a probability. The method also includes generating a random number to select from among the two or more process variation contours based on a cumulative probability value associated with each of the two or more process variation contours. The cumulative probability values are determined from the probabilities. The risk assessment or the design rule determination is performed using selected ones of the two or more process variation contours. Fabrication yield is increased based on finalizing the physical layout using the process variation contours.

Abstract: Technical solutions are described for fabricating a semiconductor wafer. An example method includes generating a process assumption band for an element of the wafer. The process assumption band depicts a shape of the element based on a set of process variations in a photolithographic process used for fabricating the wafer. The method also includes generating a process variation band for the element of the wafer based on optical process correction simulation of the photolithographic process using design rules associated with the wafer. The method also includes determining a deviation between the process assumption band and the process variation band, and recalculating one or more design rules from the design rules associated with the wafer based on the deviation. The method also includes updating the design of the wafer in response to the process variation band not being changeable to match the process assumption band, after recalculating the design rules.

Abstract: First lithography and etching are carried out on a semiconductor structure to provide a first intermediate semiconductor structure having a first set of surface features corresponding to a first portion of desired fin formation mandrels. Second lithography and etching are carried out on the first intermediate structure, using a second mask, to provide a second intermediate semiconductor structure having a second set of surface features corresponding to a second portion of the mandrels. The second set of surface features are unequally spaced from the first set of surface features and/or the features have different pitch. The fin formation mandrels are formed in the second intermediate semiconductor structure using the first and second sets of surface features; spacer material is deposited over the mandrels and is etched back to form a third intermediate semiconductor structure having a fin pattern. Etching is carried out on same to produce the fin pattern.

Abstract: Generating a layout for a multi-qubit chip is provided. A schematic is received as input. The schematic input includes a plurality of qubits, a plurality of coupling busses, a bus design parameter specifying a bus frequency, a plurality of readout busses, and a plurality of readout ports. A qubit design is selected from a qubit library, based on the qubit style in the schematic input. A bus style is selected from a bus information library, based on the bus style in the schematic input. A qubit layout is automatically generated by assembling the selected bus style/, selected qubit design, the plurality of readout busses and the plurality of readout ports.

Abstract: Verifying a quantum circuit layout design is provided. A qubit layout is received as input. The qubit layout is generated from a qubit schematic. The qubit schematic includes a plurality of qubits, a plurality of coupling buses, a plurality of readout buses, and a plurality of readout ports. Design rules checking is performed on the qubit layout input, using a predefined set of design rule. The bus style/frequency and qubit information are extracted from the qubit layout input. A new qubit schematic is generated from the extracted bus style/frequency and qubit information. The qubit layout is verified based on the new qubit schematic being the same as the qubit schematic.

Abstract: A method for semiconductor structure design includes performing, by a processor, error processing of an initial design file layout. The processor further detects a tip-to-tip (T2T) structure design violation at a design cell boundary for a metal layer above (Ma) a via (Vx) at a tip of the Ma for the initial design file layout for a semiconductor structure based on a library of pattern rules. Upon detection of the T2T structure design violation, the processor retargets the Vx for generating a resulting design file layout of the semiconductor structure.

Abstract: An apparatus including a memory storing instructions and a processor executing the instructions to perform a method including: performing error processing of an initial design file layout; detecting a tip-to-tip (T2T) structure design violation at a design cell boundary for a metal layer above (Ma) a via (Vx) at a tip of the Ma for the initial design file layout for a semiconductor structure based on a library of pattern rules; retargeting the Vx for generating a resulting design file layout of the semiconductor structure; and generating a physical semiconductor structure based on the resulting design file layout of the semiconductor structure.

Abstract: A method for structure design including a processor performing error processing of an initial design file layout. The processor detects a structure design violation at a design cell boundary for a metal layer above (Ma) a via (Vx) at a tip of the Ma for the initial design file layout for a semiconductor structure based on a library of pattern rules. Upon detection of the structure design violation, the processor retargets the Vx for generating a resulting design file layout of the semiconductor structure. A physical semiconductor structure is generated based on the resulting design file layout of the semiconductor structure.

Abstract: A technique for optimizing integrated circuit (IC) designs based on interaction between multiple integration design rules is provided. For a plurality of IC features, total risk values are determined based on multiple integration design rules. IC features are ordered based on the total risk values. IC features having the highest total risk values are selected based on a threshold count. An IC design is clipped around the high-risk IC features. An overall failure rate is simulated for the clipped area. If the overall failure rate exceeds a threshold, a predicted failure rate for each design rule that applies to IC features within the clipped area is calculated. A high-risk design rule is identified based on the predicted failure rates. The IC design is modified such that a difference between a design rule value of the high-risk design rule and a corresponding design value is reduced.

Abstract: A technique for optimizing integrated circuit (IC) designs based on interaction between multiple integration design rules is provided. For a plurality of IC features, total risk values are determined based on multiple integration design rules. IC features are ordered based on the total risk values. IC features having the highest total risk values are selected based on a threshold count. An IC design is clipped around the high-risk IC features. An overall failure rate is simulated for the clipped area. If the overall failure rate exceeds a threshold, a predicted failure rate for each design rule that applies to IC features within the clipped area is calculated. A high-risk design rule is identified based on the predicted failure rates. The IC design is modified such that a difference between a design rule value of the high-risk design rule and a corresponding design value is reduced.

Abstract: Embodiments include methods, design layout optimization systems, and computer program products for optimizing design layout of integrated circuits.

Abstract: An air gap metal tip structure is provided for ESD protection that includes a lower substrate and an upper substrate disposed above the lower substrate. The air gap metal tip structure includes a first and a second metal tip disposed along at least one horizontal axis that is parallel to the upper substrate and the lower substrate. The air gap metal tip structure includes an air chamber formed between the upper and lower substrates within which the first and second metal tips are disposed. The air chamber includes a portion between points of the metal tips. Oxygen trapped in the air chamber is converted into ozone responsive to an occurrence of an arc between the tips to dissipate the arc, and the ozone is decomposed back into the oxygen responsive to an absence of the arc between the tips to maintain the ESD protection for subsequent arcs.

Abstract: An air gap metal tip structure is provided for ESD protection that includes a lower substrate and an upper substrate disposed above the lower substrate. The air gap metal tip structure includes a first and a second metal tip disposed along at least one horizontal axis that is parallel to the upper substrate and the lower substrate. The air gap metal tip structure includes an air chamber formed between the upper and lower substrates within which the first and second metal tips are disposed. The air chamber includes a portion between points of the metal tips. Oxygen trapped in the air chamber is converted into ozone responsive to an occurrence of an arc between the tips to dissipate the arc, and the ozone is decomposed back into the oxygen responsive to an absence of the arc between the tips to maintain the ESD protection for subsequent arcs.

Abstract: A capacitive device includes a first electrode comprising a nanosheet stack and a second electrode comprising a nanosheet stack, the second electrode arranged substantially parallel to the first electrode. A first conductive contact is arranged on a basal end of the first electrode, and a second conductive contact is arranged on a basal end of the second electrode.

Abstract: A capacitive device includes a first electrode comprising a nanosheet stack and a second electrode comprising a nanosheet stack, the second electrode arranged substantially parallel to the first electrode. A first conductive contact is arranged on a basal end of the first electrode, and a second conductive contact is arranged on a basal end of the second electrode.

Abstract: A capacitive device includes a first electrode comprising a nanosheet stack and a second electrode comprising a nanosheet stack, the second electrode arranged substantially parallel to the first electrode. A first conductive contact is arranged on a basal end of the first electrode, and a second conductive contact is arranged on a basal end of the second electrode.