Abstract: A display substrate, including: a base substrate; a plurality of data lines on the base substrate; a first insulating layer on a side of the plurality of data lines away from the base substrate; a plurality of gate lines on a side of the first insulating layer away from the plurality of data lines, where extension directions of the gate and data lines are intersected; a second insulating layer on a side of the plurality of gate lines away from the first insulating layer; and a first electrode on a side of the second insulating layer away from the plurality of gate lines, where at least a portion of an orthographic projection of the first electrode on the base substrate is within an region surrounded by orthographic projections of two adjacent data lines on the base substrate and orthographic projections of two adjacent gate lines on the base substrate.

Abstract: A display apparatus includes sub-pixels, at least one gate line group and a scan drive circuit. The gate line group includes a first gate line, a second gate line and a third gate line. The scan drive circuit outputs, in a frame scan cycle, a first scan signal to the first gate line, a second scan signal to the second gate line, and a third scan signal to the third gate line in sequence. Durations of effective scan periods of the scan signals are equal. A start moment of the effective scan period of the second scan signal is delayed by a first time length compared with that of the first scan signal. A start moment of the effective scan period of the third scan signal is delayed by a second time length less than the first time length compared with that of the second scan signal.

Abstract: A display panel and a display device are disclosed. The display panel includes a gate driving circuit, a plurality of clock signal lines, a timing controller and a plurality of anti-cross-row circuits; the timing controller is configured to provide a first clock signal; the plurality of anti-cross-row circuits are connected with the timing controller and the plurality of clock signal lines, and are configured to adjust the first clock signal provided by the timing controller to a second clock signal, and output the second clock signal to the plurality of clock signal lines, and a falling duration of a falling edge of the second clock signal is less than a falling duration of a falling edge of the first clock signal; and each of the plurality of anti-cross-row circuits comprises at least one resistor and at least one inductor.

Abstract: A driving method for a display panel and a display apparatus. The driving method includes: obtaining original display data of a current display frame; and when it is determined to adopt a first driving mode, loading first gate scanning signals (GA1_1-GA12_1) to gate lines (GA, GA1-GA12) in the display panel, and loading a data voltage to data lines (DA, DA1-DA7) in the display panel according to target display data obtained by removing a part of data from the original display data, so as to charge each sub-pixel in the display panel with the data voltage.

Abstract: A driving circuit, a display device, and a driving method are disclosed. The driving circuit includes a level conversion unit and a gate electrode driving unit; and the gate electrode driving unit is configured to sequentially shift and output a plurality of first gate scan signals by a first portion of the 2n gate signal output terminals in response to a first portion of the plurality of first output signals received at a first moment by a first portion of the plurality of second clock signal input terminals, and sequentially output a plurality of second gate scan signals by a second portion of the 2n gate signal output terminals in response to a second portion of the plurality of first output signals received at a second moment by a second portion of the plurality of second clock signal input terminals.

Abstract: A driving method for a display panel and a display apparatus. The driving method includes: acquiring display data of a to-be-displayed image in a current display frame (S100); and loading a data voltage on a data line in the display panel according to the display data, such that each sub-pixel in the display panel is charged with the corresponding data voltage (S200).

Abstract: Provided are a display apparatus and a method for driving display apparatus. The display apparatus includes a display substrate; the display substrate includes: gate drive circuit, connected with gate lines disposed in the display area; a plurality of clock signal lines; and a bonding pad; a first circuit board; and a second circuit board; the first circuit board and the second circuit board are independent of each other; the first circuit board is disposed at a side, facing away from the display area, of the second circuit board; the first circuit board and the second circuit board are electrically connected with the bonding pad; the first circuit board is electrically connected with the gate drive circuit via the plurality of clock signal lines; and in an extension direction of the gate line, a width of the first circuit board is smaller than a width of the second circuit board.

Abstract: An array base plate and a display panel. The array base plate includes a substrate and a plurality of sub-pixels that are provided on the substrate and are arranged in an array; each of the sub-pixels includes a first slit electrode (1) and a second slit electrode (2) that are arranged in a first direction the first slit electrode (1) includes a plurality of first slits (11) that are arranged parallelly and separately, and the second slit electrode (2) includes a plurality of second slits (21) that are arranged parallelly and separately, and a direction of extension of the first slits (11) and a direction of extension of the second slits (21) are different; and the sub-pixel further includes a dark-region light shielding part (6) located over the first slit electrode (1) and the second slit electrode (2).

Abstract: An array substrate includes a gate drive circuit including shift register units in cascade. The driving method includes: in a first driving mode, loading a first clock signal with an active level and an inactive level alternating periodically to a cascade clock signal terminal of a shift register unit, and loading a second clock signal with an active level and an inactive level alternating periodically to any one of K drive clock signal terminals of the shift register unit; and in a second driving mode, loading the first clock signal to the cascade clock signal terminal, and loading a third clock signal with an active level appearing within a target time period to a target drive clock signal terminal among the K drive clock signal terminals so that a target drive output terminal corresponding to the target drive clock signal terminal outputs a gate turn-on signal.

Abstract: Provides are a drive method of a display panel and a display apparatus. The drive method of the display panel includes: obtaining a current temperature of the display panel; obtaining a current overdrive lookup table corresponding to the current temperature according to the current temperature and initial overdrive lookup tables corresponding to prestored set temperatures, wherein the initial overdrive lookup tables include a plurality of different first gray-scale values, a plurality of different second gray-scale values and initial gray-scale values corresponding to any first gray-scale value and any second gray-scale value, and the current overdrive lookup table includes a plurality of different first gray-scale values, a plurality of different second gray-scale values and current gray-scale values corresponding to any first gray-scale value and any second gray-scale value; and driving sub-pixels in the display panel to charge corresponding data voltages according to the current overdrive lookup table.

Abstract: A display driving method, a display driving device and a display device are provided. The display driving method includes: when displaying an odd-numbered frame, providing first parity row data of the odd-numbered frame to a display array, to enable a third parity row of the display array to be displayed based on real data of the first parity row data and enable a fourth parity row of the display array to be displayed based on interpolation data of the first parity row data; and when displaying an even-numbered frame, providing second parity row data of the even-numbered frame to the display array, to enable the fourth parity row of the display array to be displayed based on real data of the second parity row data and enable the third parity row of the display array to be displayed based on interpolation data of the second parity row data.

Abstract: Provided are a display apparatus and a method for driving display apparatus. The display apparatus includes a display substrate; the display substrate includes: gate drive circuit, connected with gate lines disposed in the display area; a plurality of clock signal lines; and a bonding pad; a first circuit board; and a second circuit board; the first circuit board and the second circuit board are independent of each other; the first circuit board is disposed at a side, facing away from the display area, of the second circuit board; the first circuit board and the second circuit board are electrically connected with the bonding pad; the first circuit board is electrically connected with the gate drive circuit via the plurality of clock signal lines; and in an extension direction of the gate line, a width of the first circuit board is smaller than a width of the second circuit board.

Abstract: A liquid crystal display panel includes a first polarizer, a second polarizer arranged opposite to the first polarizer, a liquid crystal layer, a first optical compensation layer and a second optical compensation layer. Transmission axes of the first polarizer and the second polarizer are perpendicular to each other. An orthographic projection of an optical axis of the first optical compensation layer on the first polarizer is parallel to the transmission axis of the first polarizer. An optical axis of the second optical compensation layer is perpendicular to a plane where the second optical compensation layer is located. An in-plane retardation RO1 of the first optical compensation layer and an in-plane retardation ROLC of the liquid crystal layer satisfy a formula: RO1=n1×ROLC+m1?1, in which m1 is an integer, n1 is in a range of ¼ to ¾, inclusive, and ?1 is in a range of 390 nm to 780 nm, inclusive.

Abstract: A display panel and a display device are provided. The display panel includes: an array substrate, a cell-assembling substrate, and a liquid crystal layer located therebetween. The array substrate includes a first base, and the first base comprises sub-pixel regions (A), a first trace region (B) located between two adjacent rows of sub-pixel regions (A), and a second trace region (C) located between two adjacent columns of sub-pixel regions (A). Gate lines (1) are located in the first trace region (B). Data lines (2) are located in the second trace region (C), each data line (2) has a support portion (21), and the support portion (21) is located in an intersection region of the first trace region (B) and the second trace region (C). Sub-pixel units are located in the sub-pixel region (A), and the sub-pixel units includes a common electrode (4).

Abstract: Embodiments of the present disclosure provide a display panel and a display device. The display panel includes: a base substrate including a non-display area; a gate drive circuit located in the non-display area, where the gate drive circuit includes a plurality of shift registers, and the plurality of shift registers are divided into a plurality of register sets; and a plurality of signal lead-in lines located in the non-display area, where the plurality of signal lead-in lines are divided into a plurality of line sets, a frame start signal end of one register set is correspondingly and electrically connected to one line set, and two signal lead-in lines of one line set are provided with the signal lead-in line of another line set therebetween.

Abstract: A display panel and a display device are disclosed. The display panel includes a gate driving circuit, a plurality of clock signal lines, a timing controller and a plurality of anti-cross-row circuits; the timing controller is configured to provide a first clock signal; the plurality of anti-cross-row circuits are connected with the timing controller and the plurality of clock signal lines, and are configured to adjust the first clock signal provided by the timing controller to a second clock signal, and output the second clock signal to the plurality of clock signal lines, and a falling duration of a falling edge of the second clock signal is less than a falling duration of a falling edge of the first clock signal; and each of the plurality of anti-cross-row circuits comprises at least one resistor and at least one inductor.

Abstract: A display panel, a driving method for the display panel and a display device. The display panel includes a gate driving circuit, the gate driving circuit includes shift registers of a plurality of stages arranged in sequence, the shift registers of the plurality of stages arranged in sequence are combined into N groups of gate driving sub-circuits, and shift registers in the N groups of gate driving sub-circuits are cascaded, respectively; an m-th group of gate driving sub-circuits in the N groups of gate driving sub-circuits comprises a shift register of an m-th stage and a shift register of an (m+L*N)th stage that are cascaded, where m is an integer that is greater than or equal to 1 and less than or equal to N, L is an integer that is greater than or equal to 1, N is an even number that is greater than or equal to 2.

Abstract: The present application relates to the technical field of display. Disclosed are an array substrate and a display panel. The array substrate comprises: a substrate, and scanning lines, scanning signal lines, data line pairs, thin film transistors and pixel electrodes, which are arranged on the substrate, wherein the substrate has a display area, and the display area comprises sub-pixel areas, which are distributed in an array; two adjacent scanning lines form a scanning line group, the scanning signal lines extend in a column direction, and one scanning signal line is electrically connected to only two scanning lines in one scanning line group; each data line pair comprises two data lines, sub-pixel columns are provided in one-to-one correspondence with the data line pairs, and the two data lines in each data line pair pass through corresponding sub-pixel areas in the column direction; and in a row direction, a light-shielding strip is provided between every two adjacent sub-pixel areas.

Abstract: The embodiments of the present disclosure provide a display substrate, a display panel, and a display device. The display substrate includes: a first base substrate, wherein a plurality of sub-pixel regions arranged in an array are provided on the first base substrate; and a reflective layer provided on one side of the first base substrate, wherein a surface of the reflective layer away from the first base substrate is formed to include a plurality of first bumps and a plurality of second bumps, and the first bump has a size greater than that of the second bump.

Abstract: A display driving method, a display driving device and a display device are provided. The display driving method includes: when displaying an odd-numbered frame, providing first parity row data of the odd-numbered frame to a display array, to enable a third parity row of the display array to be displayed based on real data of the first parity row data and enable a fourth parity row of the display array to be displayed based on interpolation data of the first parity row data; and when displaying an even-numbered frame, providing second parity row data of the even-numbered frame to the display array, to enable the fourth parity row of the display array to be displayed based on real data of the second parity row data and enable the third parity row of the display array to be displayed based on interpolation data of the second parity row data.