Abstract: A manufacturing method of a semiconductor device may include: forming a stack comprising first material layers and second material layers that are alternately stacked; forming an opening in the stack; forming a first seed layer in the opening; forming a first buffer layer by surface-treating the first seed layer; and forming a blocking layer by oxidizing the first seed layer through the first buffer layer.

Abstract: A monoclonal antibody or an antigen-binding fragment thereof according to an embodiment of the present invention can bind to lymphocyte-activation gene 3 (LAG-3) including a heavy chain variable region and a light chain variable region and inhibit the activity thereof. Thus it is expected to be useful for the development of immunotherapeutic agents for various disorders that are associated with LAG-3.

Abstract: Disclosed is a semiconductor device with improved electrical characteristics and a method for fabricating the same, and the method may include forming an alternating stack in which dielectric layers and sacrificial layers are alternately stacked on a substrate, forming a first through portion in the alternating stack, etching first portions of the sacrificial layers through the first through portion, to form lateral recesses between the dielectric layers, forming charge trapping layers isolated in the lateral recesses, forming a second through portion by etching the alternating stack in which second portions of the sacrificial layers remain, removing the second portions of the sacrificial layers through the second through portion, to form gate recesses that expose non-flat surfaces of the charge trapping layers, flattening the non-flat surfaces of the charge trapping layers, and forming a gate electrode that fills the gate recesses.

Abstract: A semiconductor memory device includes: a tunnel insulating layer disposed between a conductive pattern and a channel layer; a data storage layer disposed between the conductive pattern and the tunnel insulating layer, the data storage layer including a silicon nitride layer; a first blocking insulating layer disposed between the conductive pattern and the data storage layer; a second blocking insulating layer disposed between the conductive pattern and the first blocking insulating layer; and a carbon containing layer disposed at at least one position among a position between the tunnel insulating layer and the data storage layer, a position between the first blocking insulating layer and the data storage layer, a position in the tunnel insulating layer, and a position between the first blocking insulating layer and the second blocking insulating layer.

Abstract: Disclosed is a semiconductor device with improved electrical characteristics and a method for fabricating the same, and the method may include forming an alternating stack in which dielectric layers and sacrificial layers are alternately stacked on a substrate, forming a first through portion in the alternating stack, etching first portions of the sacrificial layers through the first through portion, to form lateral recesses between the dielectric layers, forming charge trapping layers isolated in the lateral recesses, forming a second through portion by etching the alternating stack in which second portions of the sacrificial layers remain, removing the second portions of the sacrificial layers through the second through portion, to form gate recesses that expose non-flat surfaces of the charge trapping layers, flattening the non-flat surfaces of the charge trapping layers, and forming a gate electrode that fills the gate recesses.

Abstract: A plurality of gate electrodes is stacked on an upper surface of a substrate in a direction perpendicular to an upper surface of the substrate. A channel region penetrates through the plurality of gate electrodes to extend perpendicularly to the upper surface of the substrate. A gate dielectric layer includes a tunneling layer, a charge storage layer and a blocking layer that are sequentially disposed between the channel region and the plurality of gate electrodes. The charge storage layer includes a plurality of doping elements and a plurality of deep level traps generated by the plurality of doping element. A concentration distribution of the plurality of doping elements in a thickness direction of the charge storage layer is non-uniform.

Abstract: A plurality of gate electrodes is stacked on an upper surface of a substrate in a direction perpendicular to an upper surface of the substrate. A channel region penetrates through the plurality of gate electrodes to extend perpendicularly to the upper surface of the substrate. A gate dielectric layer includes a tunneling layer, a charge storage layer and a blocking layer that are sequentially disposed between the channel region and the plurality of gate electrodes. The charge storage layer includes a plurality of doping elements and a plurality of deep level traps generated by the plurality of doping element. A concentration distribution of the plurality of doping elements in a thickness direction of the charge storage layer is non-uniform.

Abstract: A semiconductor device is provided as follows. A tunnel insulation layer is disposed on a substrate. The tunnel insulation layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon layer interposed between the first silicon oxide layer and the second silicon oxide layer. The silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer. A gate pattern is disposed on the tunnel insulation layer.

Abstract: A semiconductor device includes: a substrate including a channel region; a gate dielectric a tunneling layer, a charge storage layer, and a blocking layer sequentially disposed on the channel region; and a gate electrode disposed on the gate dielectric, wherein the tunneling layer has variations in nitrogen concentrations in a direction perpendicular to the channel region, and has a maximum nitrogen concentration in a position shifted from a center of the tunneling layer toward the charge storage layer.

Abstract: A semiconductor device is provided as follows. A tunnel insulation layer is disposed on a substrate. The tunnel insulation layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon layer interposed between the first silicon oxide layer and the second silicon oxide layer. The silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer. A gate pattern is disposed on the tunnel insulation layer.

Abstract: A semiconductor device is provided as follows. A tunnel insulation layer is disposed on a substrate. The tunnel insulation layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon layer interposed between the first silicon oxide layer and the second silicon oxide layer. The silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer. A gate pattern is disposed on the tunnel insulation layer.

Abstract: A vertical-type nonvolatile memory device includes a first vertical channel structure, and first and second stacked structure. The first vertical channel structure extends vertically on a substrate. The first stacked structure includes gate electrodes and first interlayer insulating layers. The gate layers and the first interlayer insulating layers are alternately and vertically stacked on each other. The first stacked structure is disposed on a first sidewall of the first vertical channel structure. The second stacked structure includes first sacrificial layers and second interlayer insulating layers. The first sacrificial layers and the second interlayer insulating layers are alternately and vertically stacked on each other. The second stacked structure is disposed on a second sidewall of the first vertical channel structure. The first sacrificial layers is formed of a polysilicon layer.

Abstract: Nonvolatile memory devices include at least four cylindrical-shaped channel regions, which extend vertically from portions of a substrate located at respective vertices of at least one rhomboid when viewed in a vertical direction relative to a surface of the substrate. A charge storage layer (e.g., ONO layer) is provided on an outer sidewall of each of the cylindrical-shaped channel regions. In addition, to achieve a high degree of integration, a plurality of vertically-stacked gate electrodes are provided, which extend adjacent each of the cylindrical-shaped channel regions.

Abstract: A semiconductor device is provided as follows. A tunnel insulation layer is disposed on a substrate. The tunnel insulation layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon layer interposed between the first silicon oxide layer and the second silicon oxide layer. The silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer. A gate pattern is disposed on the tunnel insulation layer.

Abstract: A vertical memory device including a substrate including first regions and a second region; a plurality of channels in the first regions, the plurality of channels extending in a first direction substantially perpendicular to a top surface of the substrate; a charge storage structure on a sidewall of each channel in a second direction substantially parallel to the top surface of the substrate; a plurality of gate electrodes in the first regions, the plurality of gate electrodes arranged on a sidewall of the charge storage structure and spaced apart from each other in the first direction; and a plurality of supporters in the second region, the plurality of supporters spaced apart from each other in a third direction substantially perpendicular to the first direction and the second direction, the plurality of supporters contacting a sidewall of at least one gate electrode.

Abstract: A semiconductor device includes: a substrate including a channel region; a gate dielectric a tunneling layer, a charge storage layer, and a blocking layer sequentially disposed on the channel region; and a gate electrode disposed on the gate dielectric, wherein the tunneling layer has variations in nitrogen concentrations in a direction perpendicular to the channel region, and has a maximum nitrogen concentration in a position shifted from a center of the tunneling layer toward the charge storage layer.

Abstract: A vertical memory device including a substrate including first regions and a second region; a plurality of channels in the first regions, the plurality of channels extending in a first direction substantially perpendicular to a top surface of the substrate; a charge storage structure on a sidewall of each channel in a second direction substantially parallel to the top surface of the substrate; a plurality of gate electrodes in the first regions, the plurality of gate electrodes arranged on a sidewall of the charge storage structure and spaced apart from each other in the first direction; and a plurality of supporters in the second region, the plurality of supporters spaced apart from each other in a third direction substantially perpendicular to the first direction and the second direction, the plurality of supporters contacting a sidewall of at least one gate electrode.

Abstract: Provided is a method of fabricating a semiconductor memory device. The method includes alternately stacking interlayer insulating layers and sacrificial layers on a substrate, forming a channel hole exposing the substrate through the interlayer insulating layers and the sacrificial layers, sequentially forming a blocking insulating layer, an electric charge storage layer and a channel layer on a substrate exposed on a sidewall of the channel hole and in the channel hole wherein the blocking insulating layer includes a first blocking insulating layer and a second blocking insulating layer, selectively removing the sacrificial layers to expose the first blocking insulating layer and then forming a gap, removing the first blocking insulating layer exposed in the gap, forming first blocking insulating patterns between the interlayer insulating layers and the second blocking insulating layer, and forming a gate electrode in the gap.

Abstract: Nonvolatile memory devices include at least four cylindrical-shaped channel regions, which extend vertically from portions of a substrate located at respective vertices of at least one rhomboid when viewed in a vertical direction relative to a surface of the substrate. A charge storage layer (e.g., ONO layer) is provided on an outer sidewall of each of the cylindrical-shaped channel regions. In addition, to achieve a high degree of integration, a plurality of vertically-stacked gate electrodes are provided, which extend adjacent each of the cylindrical-shaped channel regions.

Abstract: A vertical memory device includes a substrate, a first cell block and a second cell block. The substrate includes a central region and a peripheral region. At least one first cell block is on the central region. The first cell block includes a first channel and first gate lines. At least one second cell block is on the peripheral region. The second cell block includes a second channel and second gate lines. The second cell block has a width greater than a width of the first cell block. The first and second channel extend in a first direction vertical to a top surface of the substrate. The first gate lines surround the first channel and the first gate lines are spaced apart from each other in the first direction. The second gate lines surround the second channel and are spaced apart from each other in the first direction.