Patents by Inventor Dongdong Wang

Dongdong Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070209831
    Abstract: A transition layer 38 is provided on a die pad 22 of an IC chip 20 and integrated into a multilayer printed circuit board 10. Due to this, it is possible to electrically connect the IC chip 20 to the multilayer printed circuit board 10 without using lead members and a sealing resin. Also, by providing the transition layer 38 made of copper on an aluminum pad 24, it is possible to prevent a resin residue on the pad 24 and to improve connection characteristics between the die pad 24 and a via hole 60 and reliability.
    Type: Application
    Filed: May 14, 2007
    Publication date: September 13, 2007
    Applicant: IBIDEN CO., LTD.
    Inventors: Hajime Sakamoto, Dongdong Wang
  • Publication number: 20050258522
    Abstract: The present invention has for its object to provide a multilayer printed circuit board which is very satisfactory in facture toughness, dielectric constant, adhesion and processability, among other characteristics. The present invention is directed to a multilayer printed circuit board comprising a substrate board, a resin insulating layer formed on said board and a conductor circuit constructed on said resin insulating layer, wherein said resin insulating layer comprises a polyolefin resin.
    Type: Application
    Filed: July 26, 2005
    Publication date: November 24, 2005
    Inventors: Honchin En, Masayuki Hayashi, Dongdong Wang, Kenichi Shimada, Motoo Asai, Koji Sekine, Tohru Nakai, Shinichiro Ichikawa, Yukihiko Toyoda
  • Publication number: 20050157478
    Abstract: Chip capacitors 20 are provided in a printed circuit board 10. In this manner, the distance between an IC chip 90 and each chip capacitor 20 is shortened, and the loop inductance is reduced. In addition, the chip capacitors 20 are accommodated in a core substrate 30 having a large thickness. Therefore, the thickness of the printed circuit board does not become large.
    Type: Application
    Filed: February 23, 2005
    Publication date: July 21, 2005
    Applicant: IBIDEN CO., LTD.
    Inventors: Yasushi Inagaki, Motoo Asai, Dongdong Wang, Hideo Yabashi, Seiji Shirai
  • Patent number: 6909054
    Abstract: A multilayer printed circuit board has an IC chip 20 included in a core substrate 30 in advance and a transition layer 38 provided on a pad 24 of the IC chip 20. Due to this, it is possible to electrically connect the IC chip to the multilayer printed circuit board without using lead members and a sealing resin. Also, by providing the transition layer 38 made of copper on the die pad 24, it is possible to prevent resin residues on the pad 24 and to improve connection characteristics between the pad 24 and a via hole 60 and reliability.
    Type: Grant
    Filed: January 12, 2001
    Date of Patent: June 21, 2005
    Assignee: Ibiden Co., Ltd.
    Inventors: Hajime Sakamoto, Tadashi Sugiyama, Dongdong Wang, Takashi Kariya
  • Patent number: 6876554
    Abstract: Chip capacitors 20 are provided in a printed circuit board 10. In this manner, the distance between an IC chip 90 and each chip capacitor 20 is shortened, and the loop inductance is reduced. In addition, the chip capacitors 20 are accommodated in a core substrate 30 having a large thickness. Therefore, the thickness of the printed circuit board does not become large.
    Type: Grant
    Filed: September 1, 2000
    Date of Patent: April 5, 2005
    Assignee: Ibiden Co., Ltd.
    Inventors: Yasushi Inagaki, Motoo Asai, Dongdong Wang, Hideo Yabashi, Seiji Shirai
  • Publication number: 20050039948
    Abstract: A metal layer 18 is sandwiched between insulating layers 14 and 20 so that required strength is maintained. Hence it follows that the thickness of a core substrate 30 can be reduced and, therefore, the thickness of a multi-layer printed circuit board can be reduced. Formation of non-penetrating openings 22 which reach the metal layer 18 in the insulating layers 14 and 20 is simply required. Therefore, small non-penetrating openings 22 can easily be formed by applying laser beams. Thus, through holes 36 each having a small diameter can be formed.
    Type: Application
    Filed: August 19, 2004
    Publication date: February 24, 2005
    Inventors: Motoo Asai, Dongdong Wang, Takahiro Mori
  • Patent number: 6828510
    Abstract: A metal layer 18 is sandwiched between insulating layers 14 and 20 so that required strength is maintained. Hence it follows that the thickness of a core substrate 30 can be reduced and, therefore, the thickness of a multi-layer printed circuit board can be reduced. Formation of non-penetrating openings 22 which reach the metal layer 18 in the insulating layers 14 and 20 is simply required. Therefore, small non-penetrating openings 22 can easily be formed by applying laser beams. Thus, through holes 36 each having a small diameter can be formed.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: December 7, 2004
    Assignee: Ibiden Co., Ltd.
    Inventors: Motoo Asai, Dongdong Wang, Takahiro Mori
  • Publication number: 20040168825
    Abstract: A multilayer printed circuit board has an IC chip 20 included in a core substrate 30 in advance and a transition layer 38 provided on a pad 24 of the IC chip 20. Due to this, it is possible to electrically connect the IC chip to the multilayer printed circuit board without using lead members and a sealing resin. Also, by providing the transition layer 38 made of copper on the die pad 24, it is possible to prevent resin residues on the pad 24 and to improve connection characteristics between the pad 24 and a via hole 60 and reliability.
    Type: Application
    Filed: March 4, 2004
    Publication date: September 2, 2004
    Inventors: Hajime Sakamoto, Tadashi Sugiyama, Dongdong Wang, Takashi Kariya
  • Publication number: 20040160751
    Abstract: A chip capacitor 20 is provided in a core substrate 30 of a printed circuit board 10. This makes it possible to shorten a distance between an IC chip 90 and the chip capacitor 20 and to reduce loop inductance. Since the core substrate 30 is constituted by providing a first resin substrate 30a, a second resin substrate 30b and a third resin substrate 30c in a multilayer manner, the core substrate 30 can obtain sufficient strength.
    Type: Application
    Filed: February 19, 2004
    Publication date: August 19, 2004
    Applicant: IBIDEN Co., Ltd.
    Inventors: Yasushi Inagaki, Motoo Asai, Dongdong Wang, Hideo Yabashi, Seiji Shirai
  • Patent number: 6724638
    Abstract: A chip capacitor 20 is provided in a core substrate 30 of a printed circuit board 10. This makesit possible to shorten a distance between an IC chip 90 and the chip capacitor 20 and to reduce loop inductance. Since the core substrate 30 is constituted by providing a first resin substrate 30a, a second resin substrate 30b and a third resin substrate 30c in a multilayer manner, the core substrate 30 can obtain sufficient strength.
    Type: Grant
    Filed: April 25, 2001
    Date of Patent: April 20, 2004
    Assignee: Ibiden Co., Ltd.
    Inventors: Yasushi Inagaki, Motoo Asai, Dongdong Wang, Hideo Yabashi, Seiji Shirai
  • Publication number: 20040014317
    Abstract: A transition layer 38 is provided on a die pad 22 of an IC chip 20 and integrated into a multilayer printed circuit board 10. Due to this, it is possible to electrically connect the IC chip 20 to the multilayer printed circuit board 10 without using lead members and a sealing resin. Also, by providing the transition layer 38 made of copper on an aluminum pad 24, it is possible to prevent a resin residue on the pad 24 and to improve connection characteristics between the die pad 24 and a via hole 60 and reliability.
    Type: Application
    Filed: March 21, 2003
    Publication date: January 22, 2004
    Inventors: Hajime Sakamoto, Dongdong Wang
  • Patent number: 6586276
    Abstract: A passivation layer is formed over a semiconductor wafer carrying a plurality of independent circuits. The passivation layer includes openings to expose bond pads on the wafer. A conductive adhesion material is then deposited over the wafer and an optional protection layer is deposited over the conductive adhesion material. The wafer is then cut up into individual microelectronic dice. During a subsequent packaging process, one or more microelectronic dice are fixed within a package core to form a die/core assembly. Expanded bond pads are then formed over the die/core assembly. The adhesion material on each die enhances the adhesion between the expanded bond pads and the passivation material on the die. One or more metal layers are then built up over the die/core assembly to provide, for example, conductive communication between the terminals of the die and the external contacts/leads of the package.
    Type: Grant
    Filed: July 11, 2001
    Date of Patent: July 1, 2003
    Assignee: Intel Corporation
    Inventors: Steven Towle, Hajime Sakamoto, Dongdong Wang
  • Publication number: 20030015342
    Abstract: A multilayer printed circuit board has an IC chip 20 included in a core substrate 30 in advance and a transition layer 38 provided on a pad 24 of the IC chip 20. Due to this, it is possible to electrically connect the IC chip to the multilayer printed circuit board without using lead members and a sealing resin. Also, by providing the transition layer 38 made of copper on the die pad 24, it is possible to prevent resin residues on the pad 24 and to improve connection characteristics between the pad 24 and a via hole 60 and reliability.
    Type: Application
    Filed: July 17, 2002
    Publication date: January 23, 2003
    Inventors: Hajime Sakamoto, Tadashi Sugiyama, Dongdong Wang, Takashi Kariya
  • Publication number: 20030013232
    Abstract: A passivation layer is formed over a semiconductor wafer carrying a plurality of independent circuits. The passivation layer includes openings to expose bond pads on the wafer. A conductive adhesion material is then deposited over the wafer and an optional protection layer is deposited over the conductive adhesion material. The wafer is then cut up into individual microelectronic dice. During a subsequent packaging process, one or more microelectronic dice are fixed within a package core to form a die/core assembly. Expanded bond pads are then formed over the die/core assembly. The adhesion material on each die enhances the adhesion between the expanded bond pads and the passivation material on the die. One or more metal layers are then built up over the die/core assembly to provide, for example, conductive communication between the terminals of the die and the external contacts/leads of the package.
    Type: Application
    Filed: July 11, 2001
    Publication date: January 16, 2003
    Applicant: Intel Corporation
    Inventors: Steven Towle, Hajime Sakamoto, Dongdong Wang