Abstract: The present invention provides a pharmaceutical composition, comprising a novel benzyloxybenzylamine amino acid derivative, its salt, and/or solvate, as an active ingredient, that inhibits intracellular signaling pathway mediated by cytokine thymic stromal lymphopoietin (TSLP), TSLP receptor (TSLPR) and IL-7R?. The composition can be used for the prevention, treatment, or prevention and treatment of cancer, inflammatory diseases, itching, allergies, and/or immune disorders.

Abstract: The present invention relates to: a method for screening an antifungal agent, the method measuring the amount or activity of proteins involved in passage through the brain-blood barrier; a biomarker composition for diagnosing meningoencephalitis or cryptococcosis; a diagnostic kit including said composition; and a therapeutic pharmaceutical composition including an inhibitor for the protein.

Abstract: A spin transfer torque magnetic random access memory (STT-MRAM) device according to the present embodiment comprises: an STT-MRAM memory array which includes a data storage unit for storing data, a defect area address storage unit for storing an address of a defect area, and a spare area for storing data of a failed area; and a bypass determination unit which includes a volatile information storage element for storing the address of the defect area, stored in the defect area address storage unit and provided thereto, and when memory array access occurs, compares an access address with the address of the defect area stored in the volatile information storage element and causes the memory array access to bypass to the spare area.

Abstract: An operating method of a storage device includes a controller: receiving read data from a non-volatile memory; measuring a plurality of threshold voltage distributions respectively corresponding to a plurality of memory units of the non-volatile memory, based on the received read data; measuring a distribution variation between the plurality of memory units, based on the measured plurality of threshold voltage distributions; dynamically determining operation parameters for the non-volatile memory, based on the measured distribution variation; and transmitting, to the non-volatile memory, an operate command, an address, and at least one operation parameter corresponding to the address.

Abstract: A spin transfer torque magnetic random access memory (STT-MRAM) device according to the present embodiment comprises: an STT-MRAM memory array which includes a data storage unit for storing data, a defect area address storage unit for storing an address of a defect area, and a spare area for storing data of a failed area; and a bypass determination unit which includes a volatile information storage element for storing the address of the defect area, stored in the defect area address storage unit and provided thereto, and when memory array access occurs, compares an access address with the address of the defect area stored in the volatile information storage element and causes the memory array access to bypass to the spare area.

Abstract: The present invention relates to a beef-specific age determination marker containing the p21 protein, to an antibody specifically bound to bovine p21 protein, to a beef-specific age determination kit containing the antibody which is specifically bound to the bovine p21 protein, and to a method which involves detecting the bovine p21 protein through an antigen-antibody binding reaction using the antibody which is specifically bound to the bovine p21 protein serving as a beef-specific age determination marker in the muscle tissue of beef, so as to determine the age of the beef. According to the present invention, the p21 protein is significantly greatly expressed in the muscle tissue of beef, the age of which is lower than 30 months, and is hardly expressed in the muscle tissue of beef, the age of which is greater than 30 months, and thus can be valuably used as a beef-specific age determination marker.

Abstract: An operating method of a storage device includes a controller: receiving read data from a non-volatile memory; measuring a plurality of threshold voltage distributions respectively corresponding to a plurality of memory units of the non-volatile memory, based on the received read data; measuring a distribution variation between the plurality of memory units, based on the measured plurality of threshold voltage distributions; dynamically determining operation parameters for the non-volatile memory, based on the measured distribution variation; and transmitting, to the non-volatile memory, an operate command, an address, and at least one operation parameter corresponding to the address.

Abstract: A memory module set includes a main integrated circuit (IC) for transmitting and receiving an electrical signal, a first group of memory modules including at least one memory module having a first pin unit connected to the main IC, and a second group of memory modules including at least one memory module having a second pin unit connected to the main IC. The groups of memory modules and the main IC are arrayed in a first direction on a substrate, and the second group of memory modules is offset with respect to the first group of memory modules in a second direction that is perpendicular to the first direction so as to have a position relative to the main IC in the second direction that is different from that of the first group of memory modules.

Abstract: The present invention relates to a beef-specific age determination marker containing the p21 protein, to an antibody specifically bound to bovine p21 protein, to a beef-specific age determination kit containing the antibody which is specifically bound to the bovine p21 protein, and to a method which involves detecting the bovine p21 protein through an antigen-antibody binding reaction using the antibody which is specifically bound to the bovine p21 protein serving as a beef-specific age determination marker in the muscle tissue of beef, so as to determine the age of the beef. According to the present invention, the p21 protein is significantly greatly expressed in the muscle tissue of beef, the age of which is lower than 30 months, and is hardly expressed in the muscle tissue of beef, the age of which is greater than 30 months, and thus can be valuably used as a beef-specific age determination marker.

Abstract: A semiconductor storage device and a method of throttling performance of the same are provided. The semiconductor storage device includes a non-volatile memory device; and a controller configured to receive a write command from a host and program write data received from the host to the non-volatile memory device in response to the write command. The controller inserts idle time after receiving the write data from the host and/or after programming the write data to the non-volatile memory device.

Abstract: A memory module set includes a main integrated circuit (IC) for transmitting and receiving an electrical signal, a first group of memory modules including at least one memory module having a first pin unit connected to the main IC, and a second group of memory modules including at least one memory module having a second pin unit connected to the main IC. The groups of memory modules and the main IC are arrayed in a first direction on a substrate, and the second group of memory modules is offset with respect to the first group of memory modules in a second direction that is perpendicular to the first direction so as to have a position relative to the main IC in the second direction that is different from that of the first group of memory modules.

Abstract: A storage device includes a data storage having first and second storage areas corresponding to different physical addresses. First data are stored in the first storage area. The storage device further includes a first memory that stores a reference count associated with the first data, and a controller that rearranges the first data from the first storage area to the second storage area in response to a change in the reference count of the first data.

Abstract: Integrated circuit systems include a non-volatile memory device (e.g, flash EEPROM device) and a memory processing circuit. The memory processing circuit is electrically coupled to the non-volatile memory device. The memory processing circuit is configured to reallocate addressable space within the non-volatile memory device. This reallocation is performed by increasing a number of physical addresses within the non-volatile memory device that are reserved as redundant memory addresses, in response to a capacity adjust command received by the memory processing circuit.

Abstract: A non-volatile memory may include a plurality of map blocks for storing a plurality of map units, the map units representing mapping information between physical addresses and logical addresses. A storage device may include such a non-volatile memory. A method of mapping such a non-volatile memory may include writing historical information regarding locations of valid map units among the map units included in map blocks previously allocated among the map blocks when a new map block among the map blocks is allocated, the valid map units representing valid mapping information, and constructing a map table including all of the valid mapping information based on the historical information and a result of searching a map block recently allocated among the map blocks.

Abstract: Integrated circuit systems include a non-volatile memory device (e.g, flash EEPROM device) and a memory processing circuit. The memory processing circuit is electrically coupled to the non-volatile memory device. The memory processing circuit is configured to reallocate addressable space within the non-volatile memory device. This reallocation is performed by increasing a number of physical addresses within the non-volatile memory device that are reserved as redundant memory addresses, in response to a capacity adjust command received by the memory processing circuit.

Abstract: A storage device includes a data storage having first and second storage areas corresponding to different physical addresses. First data are stored in the first storage area. The storage device further includes a first memory that stores a reference count associated with the first data, and a controller that rearranges the first data from the first storage area to the second storage area in response to a change in the reference count of the first data.

Abstract: The present invention relates to a beef-specific age determination marker containing the p21 protein, to a beef-specific age determination kit containing an antibody which is specifically bound to the p21 protein, and to a method which involves detecting the p21 protein through an antigen-antibody binding reaction using an antibody which is specifically bound to the p21 protein serving as a beef-specific age determination marker in the muscle tissue of beef, so as to determine the age of the beef. According to the present invention, the p21 protein is significantly greatly expressed in the muscle tissue of beef, the age of which is lower than 30 months, and is hardly expressed in the muscle tissue of beef, the age of which is greater than 30 months, and thus can be valuably used as a beef-specific age determination marker.

Abstract: Integrated circuit systems include a non-volatile memory device (e.g, flash EEPROM device) and a memory processing circuit. The memory processing circuit is electrically coupled to the non-volatile memory device. The memory processing circuit is configured to reallocate addressable space within the non-volatile memory device. This reallocation is performed by increasing a number of physical addresses within the non-volatile memory device that are reserved as redundant memory addresses, in response to a capacity adjust command received by the memory processing circuit.

Abstract: Integrated circuit systems include a non-volatile memory device (e.g, flash EEPROM device) and a memory processing circuit. The memory processing circuit is electrically coupled to the non-volatile memory device. The memory processing circuit is configured to reallocate addressable space within the non-volatile memory device. This reallocation is performed by increasing a number of physical addresses within the non-volatile memory device that are reserved as redundant memory addresses, in response to a capacity adjust command received by the memory processing circuit.

Abstract: Integrated circuit systems include a non-volatile memory device (e.g, flash EEPROM device) and a memory processing circuit. The memory processing circuit is electrically coupled to the non-volatile memory device. The memory processing circuit is configured to reallocate addressable space within the non-volatile memory device. This reallocation is performed by increasing a number of physical addresses within the non-volatile memory device that are reserved as redundant memory addresses, in response to a capacity adjust command received by the memory processing circuit.